Texas Instruments TMS570LS0714, Руководство пользователя

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TMS570LS0714
SPNS226E – JUNE 2013 – REVISED NOVEMBER 2016 www.ti.com
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Peripheral Information and Electrical Specifications
Copyright © 2013–2016, Texas Instruments Incorporated
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2) t
c(VCLK)
= interface clock cycle time = 1 / f
(VCLK)
(3) For rise and fall timings, see Table 7-2 .
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: t
c(SPC)M
≥
(PS +1)t
c(VCLK)
≥
40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: t
c(SPC)M
= 2t
c(VCLK)
≥ 40 ns.
The external load on the SPICLK pin must be less than 60 pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register.
7.12.4 MibSPI/SPI Master Mode I/O Timing Specifications
Table 7-36. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output,
SPISIMO = output, and SPISOMI = input)
(1) (2) (3)
NO. PARAMETER MIN MAX UNIT
1 t
c(SPC)M
Cycle time, SPICLK
(4)
40 256t
c(VCLK)
ns
2
(5)
t
w(SPCH)M
Pulse duration, SPICLK high (clock
polarity = 0)
0.5t
c(SPC)M
– t
r(SPC)M
– 3 0.5t
c(SPC)M
+ 3
ns
t
w(SPCL)M
Pulse duration, SPICLK low (clock
polarity = 1)
0.5t
c(SPC)M
– t
f(SPC)M
– 3 0.5t
c(SPC)M
+ 3
3
(5)
t
w(SPCL)M
Pulse duration, SPICLK low (clock
polarity = 0)
0.5t
c(SPC)M
– t
f(SPC)M
– 3 0.5t
c(SPC)M
+ 3
ns
t
w(SPCH)M
Pulse duration, SPICLK high (clock
polarity = 1)
0.5t
c(SPC)M
– t
r(SPC)M
– 3 0.5t
c(SPC)M
+ 3
4
(5)
t
d(SPCH-SIMO)M
Delay time, SPISIMO valid before
SPICLK low (clock polarity = 0)
0.5t
c(SPC)M
– 6
ns
t
d(SPCL-SIMO)M
Delay time, SPISIMO valid before
SPICLK high (clock polarity = 1)
0.5t
c(SPC)M
– 6
5
(5)
t
v(SPCL-SIMO)M
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)
0.5t
c(SPC)M
– t
f(SPC)
– 4
ns
t
v(SPCH-SIMO)M
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)
0.5t
c(SPC)M
– t
r(SPC)
– 4
6
(5)
t
su(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK
low (clock polarity = 0)
t
f(SPC)
+ 2.2
ns
t
su(SOMI-SPCH)M
Setup time, SPISOMI before SPICLK
high (clock polarity = 1)
t
r(SPC)
+ 2.2
7
(5)
t
h(SPCL-SOMI)M
Hold time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
10
ns
t
h(SPCH-SOMI)M
Hold time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
10
8
(6)
t
C2TDELAY
Setup time CS active
until SPICLK high
(clock polarity = 0)
CSHOLD = 0
C2TDELAY*t
c(VCLK)
+ 2*t
c(VCLK)
- t
f(SPICS)
+ t
r(SPC)
– 7
(C2) * t
c(VCLK)
-
t
f(SPICS)
+ t
r(SPC)
+ 5.5
ns
CSHOLD = 1
C2TDELAY*t
c(VCLK)
+ 3*t
c(VCLK)
- t
f(SPICS)
+ t
r(SPC)
– 7
(C3) * t
c(VCLK)
-
t
f(SPICS)
+ t
r(SPC)
+ 5.5
Setup time CS active
until SPICLK low
(clock polarity = 1)
CSHOLD = 0
C2TDELAY*t
c(VCLK)
+ 2*t
c(VCLK)
- t
f(SPICS)
+ t
f(SPC)
– 7
(C2) * t
c(VCLK)
-
t
f(SPICS)
+ t
f(SPC)
+ 5.5
CSHOLD = 1
C2TDELAY*t
c(VCLK)
+ 3*t
c(VCLK)
- t
f(SPICS)
+ t
f(SPC)
– 7
(C3) * t
c(VCLK)
-
t
f(SPICS)
+ t
f(SPC)
+ 5.5
9
(6)
t
T2CDELAY
Hold time SPICLK low until CS inactive
(clock polarity = 0)
0.5*t
c(SPC)M
+
T2CDELAY*t
c(VCLK)
+ t
c(VCLK)
-
t
f(SPC)
+ t
r(SPICS)
- 7
0.5*t
c(SPC)M
+
T2CDELAY*t
c(VCLK)
+ t
c(VCLK)
-
t
f(SPC)
+ t
r(SPICS)
+ 11
ns
Hold time SPICLK high until CS
inactive (clock polarity = 1)
0.5*t
c(SPC)M
+
T2CDELAY*t
c(VCLK)
+ t
c(VCLK)
-
t
r(SPC)
+ tr(SPICS) - 7
0.5*t
c(SPC)M
+
T2CDELAY*t
c(VCLK)
+ t
c(VCLK)
-
t
r(SPC)
+ t
r(SPICS)
+ 11
10 t
SPIENA
SPIENAn Sample point
(C1) * t
c(VCLK)
-
t
f(SPICS)
– 29
(C1)*t
c(VCLK)
ns
11 t
SPIENAW
SPIENAn Sample point from write to
buffer
(C2)*t
c(VCLK)
ns