Advisory
During DCAN FIFO Mode, Received Messages May be Placed Out of Order in the
FIFO Buffer
Revisions Affected
0, A, B
Details
In DCAN FIFO mode, received messages with the same arbitration and mask IDs are
supposed to be placed in the FIFO in the order in which they are received. The CPU then
retrieves the received messages from the FIFO via the IF1/IF2 interface registers. Some
messages may be placed in the FIFO out of the order in which they were received. If the
order of the messages is critical to the application for processing, then this behavior will
prevent the proper use of the DCAN FIFO mode.
Workaround
Use the DMA to read out the FIFO via the IF3 register. Each time a message is received
into the FIFO, the data is also copied to the IF3 register, and a DMA request Is generated
to the DMA module to read out the data.
Silicon Revision B Usage Notes and Advisories
SPRZ439G – JANUARY 2017 – REVISED AUGUST 2022
TMS320F28004x Real-Time MCUs Silicon Errata
Silicon Revisions B, A, 0
27
Copyright © 2022 Texas Instruments Incorporated
