Advisory
eQEP: Position Counter Incorrectly Reset on Direction Change During Index
Revisions Affected
0, A, B
Details
While using the PCRM = 0 configuration, if the direction change occurs when the index
input is active, the position counter (QPOSCNT) could be reset erroneously, resulting
in an unexpected change in the counter value. This could result in a change of up
to ±4 counts from the expected value of the position counter and lead to unexpected
subsequent setting of the error flags.
While using the PCRM = 0 configuration [that is, Position Counter Reset on Index Event
(QEPCTL[PCRM] = 00)], if the index event occurs during the forward movement, then
the position counter is reset to 0 on the next eQEP clock. If the index event occurs
during the reverse movement, then the position counter is reset to the value in the
QPOSMAX register on the next eQEP clock. The eQEP peripheral records the occurrence
of the first index marker (QEPSTS[FIMF]) and direction on the first index event marker
(QEPSTS[FIDF]) in QEPSTS registers. It also remembers the quadrature edge on the
first index marker so that same relative quadrature transition is used for index event reset
operation.
If the direction change occurs while the index pulse is active, the module would still
continue to look for the relative quadrature transition for performing the position counter
reset. This results in an unexpected change in the position counter value.
The next index event without a simultaneous direction change will reset the counter
properly and work as expected.
Workaround
Do not use the PCRM = 0 configuration if the direction change could occur while the
index is active and the resultant change of the position counter value could affect the
application.
Other options for performing position counter reset, if appropriate for the application [such
as Index Event Initialization (IEI)], do not have this issue.
Advisory
eQEP: eQEP Inputs in GPIO Asynchronous Mode
Revisions Affected
0, A, B
Details
If any of the eQEP input pins are configured for GPIO asynchronous input mode via the
GPxQSELn registers, the eQEP module may not operate properly because the eQEP
peripheral assumes the presence of external synchronization to SYSCLKOUT on inputs to
the module. For example, QPOSCNT may not reset or latch properly, and pulses on the
input pins may be missed.
For proper operation of the eQEP module, input GPIO pins should be configured via the
GPxQSELn registers for synchronous input mode (with or without qualification), which
is the default state of the GPxQSEL registers at reset. All existing eQEP peripheral
examples supplied by TI also configure the GPIO inputs for synchronous input mode.
The asynchronous mode should not be used for eQEP module input pins.
Workaround
Configure GPIO inputs configured as eQEP pins for non-asynchronous mode (any
GPxQSELn register option except “11b = Asynchronous”).
Silicon Revision B Usage Notes and Advisories
SPRZ439G – JANUARY 2017 – REVISED AUGUST 2022
TMS320F28004x Real-Time MCUs Silicon Errata
Silicon Revisions B, A, 0
15
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