TMS320F280x SDFlash Programming Utilities
F280x SDFlash Algo V1.1
Texas Instruments Inc. 15
7.2.
Specify the required PLLCR (PLL Control Register) value.
In CCS, open and modify SDFlash280x_Wrapper.h to specify the PLLCR (PLL Control Register) value.
Uncomment the line corresponding to the required PLL Control Register (PLLCR) setting. This is done
by removing the leading // in front of the correct line. Only one line should be uncommented.
For example: To have the algorithms initialize the PLLCR register to 0x0009 uncomment the second
line and comment out the remaining lines as shown:
// #define PLLCR_VALUE 0x000A // SYSCLKOUT = (OSCLK*10)/2
#define PLLCR_VALUE 0x0009
// SYSCLKOUT = (OSCLK*9)/2
// #define PLLCR_VALUE 0x0008 // SYSCLKOUT = (OSCLK*8)/2
etc …..
7.3.
Specify the clock rate of the CPU (SYSCLKOUT) in nanoseconds. In CCS, open and modify the
API configuration file Flash280x_API_Config.h to specify the clock rate of the CPU (SYSCLKOUT) in
nanoseconds. This is done by removing the leading // in front of the correct line. Only one line should
be uncommented. The file lists a number of commonly occurring clock rates. If your CPU clock rate is
not listed, then provide your own definition using the examples as a guideline.
For example: Suppose the final CPU clock rate will be 80 Mhz. This corresponds to a 12.5 nS cycle
time. There is no line present for this clock speed, so you should insert your own entry and comment
out all other entries:
//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT)
#define CPU_RATE 12.5000L // for a 80MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT)
etc…..
CAUTION
For flash integrity at operating frequencies, the device should always be programmed
at the fastest possible CPU frequency. For example, if the CLKIN frequency is 20 MHz
program the device at 100 MHz rather then 10 MHz or 20 MHz.
The flash utilities are not designed to function properly below 10 MHz.
