Hardware description
12
SLLU216 – July 2019
Copyright © 2019, Texas Instruments Incorporated
SPI to CAN FD SBC + LIN Transceiver BoosterPack User's Guide
NOTE:
Due to needing multiples of 32 bits on each SPI transaction the device should be wired for
parallel operation of the SPI as a bus with control to the device via nCS and not as a daisy
chain of shift registers.
Pin 15 of the LanchPad board-to-board header is used for the SPI SDI as is defined in the LaunchPad and
BoosterPack pinout standard as SPI_MOSI.
2.4.2.4
SPI Slave Data Output (SDO)
This pin is high impedance until the SPI output is enabled via nCS. Once the SPI is enabled by a low on
nCS, the SDO is immediately driven high or low showing the Global Fault Flag status which is also the
first bit (bit 32) to be shifted out if the SPI is clocked. Once SCLK begins, on the first low to high edge of
the clock the SDO retains the Global Fault Flag which is bit 31 of the shift. On the first falling edge of
SCLK, the shifting out of the data continues with each falling edge on SCLK until all 32 bits have been
shifted out the shift register.
Pin 14 of the LanchPad board-to-board header is used for the SPI SDO as is defined in the LaunchPad
and BoosterPack pinout standard as SPI_MISO.
2.4.3
TCAN4550-Q1 Interrupt (nINT)
The nINT is a dedicated open drain global interrupt output pin. This pin needs an external pull-up resistor
to V
IO
to function properly. All interrupt requests are reflected by this pin when pulled low.
In test mode this pin is used as an EN pin input for testing the CAN transceiver and referenced as
EN_INT. When this pin is high the device is in normal mode and when low it is in standby mode. This is
accomplished by writing 0 to register 16'h0800[0].
NOTE:
This pin is an active low and is the logical OR of all faults in registers 16'h0820 and 16'h0824
that are not masked.
Pin 31 of the LaunchPad connection header is connected to the nINT pin. Furthermore, since nINT is an
interrupt status pin, an LED has also been added to this pin as a visual indicator to the user on the status
of this pin and buffered through a transistor to prevent excessive loading on the device pin. However,
since the nINT is a negative logic indicator, the signal is first inverted through an additional transistor such
that the LED is illuminated when the nINT pin is low indicating a device interrupt has occurred.
2.4.4
TCAN4550-Q1 General Purpose Output (GPO2)
The GPO2 pin is an open drain configurable output function pin that provides selected interrupts. This pin
needs an external pull-up resistor to V
IO
to function properly. The output function can be changed by using
register 16'h0800[23:22] and can be configured as a watchdog output reset pin.
In test mode this pin becomes the RXD_INT_PHY transceiver output or TXD_INT_CAN CAN controller
output pin.
Pin 32 of the LaunchPad connection header is connected to the GPO2 pin. Furthermore, since GPO2 can
be used as an interrupt status pin, an LED has also been added to this pin as a visual indicator to the user
on the status of this pin and buffered through a transistor to prevent excessive loading on the device pin.
However, since the GPO2 is a negative logic indicator when used for interrupts, the signal is first inverted
through an additional transistor such that the LED is illuminated when the GPO2 pin is low indicating a
device interrupt has occurred.
2.4.5
TCAN4550-Q1 General Purpose Input/Output (GPIO1)
This pin defaults out as the M_CAN_INT 1 (active low) interrupt. The functionality of the pin can be
changed to a configurable output function pin by setting register 16'h0800[15:14] = 00. The GPO function
is further configured by using register 16'h0800[11:10]. To configure the pin to support a watchdog input
timer reset pin use SPI register 16'h0800[15:14] = 10.
