Hardware description
11
SLLU216 – July 2019
Copyright © 2019, Texas Instruments Incorporated
SPI to CAN FD SBC + LIN Transceiver BoosterPack User's Guide
2.4.2
TCAN4550-Q1 SPI
The SPI communication uses a standard SPI interface. Physically the digital interface pins are nCS (Chip
Select Not), SDI (Slave Data In), SDO (Slave Data Out) and SCLK (SPI Clock). Each SPI transaction is a
32 bit word containing a command byte followed by two address bytes and length bytes. The data shifted
out on the SDO pin for the transaction always starts with the Global Status Register (byte). This register
provides the high level status information about the device status. The two data bytes which are the
'response' to the command byte are shifted out next. Data bytes shifted out during a write command is
content of the registers prior to the new data being written and updating the registers. Data bytes shifted
out during a read command are the current content of the registers and the registers is not updated.
The SPI input data on SDI is sampled on the low to high edge of the SCLK. The SPI output data on SDO
is changed on the high to low edge of the SCLK.
2.4.2.1
Chip Select Not (nCS)
This input pin is used to select the device for a SPI transaction. The pin is active low, so while nCS is high
the SDO pin of the device is high impedance allowing a SPI bus to be shared with other devices. When
nCS is low the SDO driver is activated and communication may be started. The nCS pin must be held low
for the duration of the SPI transaction. A special feature on this device allows the SDO pin to immediately
show the Global Fault Flag on a falling edge of nCS.
There are two pins in the LaunchPad and BoosterPack pinout standard that could be used for the SPI
Chip Select defined as SPI_CS. Both of these pins are supported on the BoosterPack with the header pin
13 connected to the TCAN4550-Q1 nCS pin by default. If there is a conflict with this pin the other
supported chip select pin can be used by removing the 0-
Ω
resistor R21 and installing it on R57 instead.
These pins are labeled on the BoosterPack nCS_0 and nCS_1 next to pins 12 and 13 of the LaunchPad
board-to-board headers.
NOTE:
The Chip Select signal must transition back to a high following the end of the data
transaction and cannot be held low indefinitely as is sometimes common practice when only
a single device is on the SPI bus. There are 2 primary reasons for this:
1.) The Global Status Register (byte) is always shifted out on the SDO pin for every SPI
transaction starting with the first clock cycle following the chip select high-to-low transition.
2.) The device counts the number of bits received on the SDI pin which must be a multiple of
32 bits between the chip select transition to low at the beginning of the transaction and then
back to high at the completion of the transaction. If the number of bits is not a multiple of 32
bits, the last word of the transfer is ignored and the SPIERR flag is set.
2.4.2.2
SPI Clock Input (SCLK)
This input pin is used to input the clock for the SPI to synchronize the input and output serial data bit
streams. The SPI Data Input is sampled on the rising edge of SCLK and the SPI Data Output is changed
on the falling edge of the SCLK.
Pin 7 of the LanchPad board-to-board header is used for the SPI SCLK as is defined in the LaunchPad
and BoosterPack pinout standard as SPI_CLK.
2.4.2.3
SPI Slave Data Input (SDI)
This input pin is used to shift data into the device. Once the SPI is enabled by a low on nCS the SDI
samples the input shifted data on each rising edge of the SCLK. The data is shifted into a 32 bit shift
register. If the command code was a write, the new data is written into the addressed register only after
exactly 32 bits have been shifted in by SCLK and the nCS has a rising edge to deselect the device. If
there are not exactly a multiple of 32 bits shifted in to the device during one SPI transaction (nCS low) the
last word of the transfer is ignored, the SPIERR flag is set.
