Data
N 16 16
u
u
TLC6946 Design Example
41
SLVUBF4A – February 2018 – Revised June 2019
Copyright © 2018–2019, Texas Instruments Incorporated
Device Operation Examples
TI Information — Selective Disclosure
Table 4-8. Function-Control Registers For Blue Color LEDs
FUNCTION-CONTROL
REGISTER
REGISTER VALUE (BIN)
REGISTER VALUE (HEX)
FC1
0110 0110 0000 1000b
6608h
FC2
0100 0010 0100 0001b
4021h
FC3
0000 1100 1110 1010b
0CEAh
FC4
0000 0000 0000 0000b
0000h
4.1.2.2
Send FC Register Data to theTLC6946 Device
NOTE:
The WRTFC_EN command must always be input before writing function-control data to
devices.
Sending function-control register data to the TLC6946 device follows the steps below:
1. WRTFC_EN: Pull up the LAT signal, and then pull down the LAT signal after 15 SCLK rising edges
to enable the write FC data function.
2. WRTFC1: Shift the FC1 register data from SIN into the common shift registers of the devices with
the SCLK rising edge. Pull up the LAT signal before the last 5 SCLK rising edges, and pull down the
LAT signal after the last SCLK rising edge. At the same time as the last SCLK falling edge, the FC1
data is latched into the FC1 register. In this example, there are 15 TLC6946 devices cascaded, and a
total of 240 SCLK rising edges are required to shift the correct FC1 register value to all devices.
3. WRTFC2: Shift the FC2 register data from SIN into the common shift registers of the devices with
the SCLK rising edge. Pull up the LAT signal before the last 7 SCLK rising edges, and pull down the
LAT signal after the last SCLK rising edge. At the same time as the last SCLK falling edge, the FC2
data is latched into the FC2 register. The same as WRTFC1, there are 15 TLC6946 devices cascaded
in this example, and a total of 240 SCLK rising edges are required to shift the FC2 register data to all
devices.
4. WRTFC3: Shift the FC3 register data from SIN into the common shift registers of the devices with
the SCLK rising edge. Pull up the LAT signal before the last 9 SCLK rising edges, and pull down the
LAT signal after the last SCLK rising edge. At the same time as the last SCLK falling edge, the FC3
data is latched into the FC3 register. The same as WRTFC1, there are 15 TLC6946 devices cascaded
in this example, and a total of 240 SCLK rising edges are required to shift the FC3 register data to all
devices.
5. WRTFC4: Shift the FC4 register data from SIN into the common shift registers of the devices with
the SCLK rising edge. Pull up the LAT signal before the last 11 SCLK rising edges, and pull down the
LAT signal after the last SCLK rising edge. At the same time as the last SCLK falling edge, the FC4
data is latched into the FC4 register. The same as WRTFC1, there are 15 TLC6946 devices cascaded
in this example, and a total of 240 SCLK rising edges are required to shift the FC4 register data to all
devices.
4.1.3 PWM Grayscale Control
After all the FC registers are configured, send the grayscale (GS) data and GCLK clock signal to start the
frame image display.
4.1.3.1
Send GS Data to the TLC6946 Device
Sending GS data to the TLC6946 device follows the procedure below.
shows how to calculate
the total number of GS data bits to send to the device for each GS data latch operation.
where
N is the number of cascaded TLC6946 devices
(5)