WRTGS
WRTGS
WRTGS
Line Counter
(Internal bit)
Channel Counter
(Internal bit)
0
1
15
0
1
15
WRTGS
WRTGS
WRTGS
0
1
2
0
Input Command
WRTGS
WRTGS
WRTGS
Line Counter
(Internal bit)
Channel Counter
(Internal bit)
0
1
15
0
1
WRTGS
WRTGS
31
0
Input Command
Channel counter value is increased by 1
for each WRTGS command input
Line address counter value is increased by 1
when channel address counter is reset to 0
Line address counter value is reset to 0 when it reached the maximum scan
line number set in FC3 (in this example, there are total 32 scan lines)
2
Write Grayscale Data into Selected Memory Bank:
Write Grayscale Data Into Memory
30
SLVUBF4A – February 2018 – Revised June 2019
Copyright © 2018–2019, Texas Instruments Incorporated
PWM Grayscale Control
TI Information — Selective Disclosure
3.1.4 Write Grayscale Data Into One Memory BANK
After power on, the TLC694x internal registers and counters, BANK_SEL, LINE_WRITE_COUNTER, and
CHANNEL_COUNTER, are all initialized to 0. Thus, the memory unit of BANK A, line 0, channel 0 is
selected to be written with the data in the common shift register for line 0, channel 0 LED of the TLC694x
device.
When the first WRTGS command is received, all the data in the common shift register is latched into the
memory unit of BANK A, line 0, channel 0 at the falling edge of LAT. At the same time,
CHANNEL_COUNTER increments by 1 and LINE_WRITE_COUNTER stays the same. Thus, the memory
unit of BANK A, line 0, channel 1 is selected to be written with the data in the common shift register for the
line 0, channel 1 LED of the TLC694x device.
When the second WRTGS command is received, all the data in the common shift register is latched into
the memory unit of BANK A, line 0, channel 1 at the falling edge of LAT. At the same time,
CHANNEL_COUNTER increments by 1 and LINE_WRITE_COUNTER stays the same. Thus, the memory
unit of BANK A, line 0, channel 2 is selected to be written with the data in the common shift register for the
line 0, channel 2 LED of the TLC694x device.
Repeat the grayscale-data-write operation until the 16th WRTGS command is received. Then, all the data
in the common shift register are latched into the memory unit of BANK A, line 0, channel 15 at the falling
edge of LAT. At the same time, CHANNEL_COUNTER is reset to 0 and LINE_WRITE_COUNTER
increments by 1. Thus, the memory unit of BANK A, line 1, channel 0 is selected to be written with the
data in the common shift register for the line 1, channel 0 LED of the TLC694x device. All LED grayscale
data of line 0 are latched into the internal memory unit, and the TLC694x device starts to latch the LED
grayscale data of line 1.
Repeat this operation for each line until the line counter exceeds the number of scan lines set in the FC3
register (see
) and all scan lines have been updated with new GS data, which means one frame
of GS data is loaded into the memory BANK. Then the line counter is reset to 0. See
for the
timing diagram.
Figure 3-4. Write Grayscale Data Into Selected Memory BANK
3.2
Vertical Frame Synchronization (VSYNC)
3.2.1 VSYNC Command
VSYNC is the vertical frame synchronization command. When the period of one frame ends, send this
command to exchange the usage of the two memory BANKs, then the new image in the other BANK is
displayed in the coming frame period.
