Texas Instruments TL16C750EEVM Скачать руководство пользователя страница 13

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GND

LDO OUT

VCC

TP19

TP20

3.3V

GND

J26

5V INPUT

J27

GND

R109

GND

OUT

GND

TPS70633DBVR

U10

50V

1uF

C20

GND

16V

2.2uF

C23

J28

4.7k

R107

110

R105

GND

25V

0.01uF

C22

25V

0.1uF

C21

Iout MAX = 150mA

J29

3.3V

R110

DNP

LDO OUT

VCC

J10

VUART

3.3V

R108

SH-J29

www.ti.com

Schematic and Bill of Materials

SLLU317 – January 2020

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TL16C750EEVM User's Guide

Figure 13. Schematic page 2

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Содержание TL16C750EEVM

Страница 1: ...EVM with the DUT at 3 3 V or lower 6 6 Loopback mode 7 7 Mode Select 9 8 Reset 10 9 Silkscreen Errors on EVM 10 10 Board Layout 11 11 Schematic and Bill of Materials 12 List of Figures 1 High to low s...

Страница 2: ...EVM for evaluation 2 5 V Processor to 3 3 V VCC on TL16C750E The below sections describes how to set up the EVM when using a 5 V digital logic processor to interface with the TL16C750E used at a 3 3 V...

Страница 3: ...slation Header denoted as J2 allows for the bidirectional data pins D0 D7 to be accessed The 5 V input pins RESET A0 A1 A2 CS IOW and IOR can be accessed at J22 The INT TXRDY and RXRDY lines each have...

Страница 4: ...he expected voltage on the input power J26 is 5 V as this is a common processor voltage range a larger voltage should not be used The input voltage can be lower depending on VDO of the LDO this is out...

Страница 5: ...oted on the EVM as U10 For the 3 3 V regulator to be selected to provide power to the TL16C750E and onboard level shifters J29 must be configured such that position 2 and position 3 are shunted togeth...

Страница 6: ...ition 1 and 2 where the board denotes if VUART 3V6 J30 should be shunted from position 2 and 3 where the board denotes if VUART 3V6 Jumpers denoted as J9 J25 J29 J24 and J19 should not have shunts Fig...

Страница 7: ...s INT TXRDY and RXRDY J12 allow access to the bidirectional data pins D0 D7 J14 are for the input pins RESET A0 A1 A2 CS IOW and IOR J18 provides access to the inputs RI CD DSR CTS and RX Finally J13...

Страница 9: ...unted or shunted at position 2 and 3 the TL16C750E is in Intel mode This requires lines CS IOW and IOR to be used to read or write from the device If positions 1 and 2 are shunted on J1 Motorola mode...

Страница 10: ...1 and 2 and J14 position 1 and 2 by toggling the logic level Driving the logic level low places the device in reset Alternatively a hardware reset switch is provided and denoted as S1 A reset is obse...

Страница 11: ...w ti com Board Layout 11 SLLU317 January 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated TL16C750EEVM User s Guide 10 Board Layout Figure 10 EVM top Figure 11 EVM bott...

Страница 12: ...0 1 F C3 50V 0 01 F C5 0 R56 0 R53 0 R59 DNP MR RESET MR RESET 30 R41 CD DSR CTS CD DSR CTS CD_5V DSR_5V CTS_5V CD_5V DSR_5V CTS_5V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 J2 D0_5V D1_5V D2_5V D3_5V D4...

Страница 13: ...01uF C22 25V 0 1uF C21 D5 Iout MAX 150mA 1 2 3 J29 3 3V 0 R110 DNP LDO OUT VCC D7 J10 VUART 3 3V 0 R108 SH J29 www ti com Schematic and Bill of Materials 13 SLLU317 January 2020 Submit Documentation F...

Страница 14: ...CAP CERM 0 01 uF 25 V 5 C0G NP0 0603 0603 C0603H103J3GACTU Kemet C23 1 2 2uF CAP CERM 2 2 uF 16 V 10 X5R 0805 0805 EMK212BJ225KG T Taiyo Yuden D1 D4 2 Yellow LED Yellow SMD LED 1 3x0 65x0 8mm LY L29K...

Страница 15: ...MOSFET N CH 50 V 0 2 A SOT 23 SOT 23 RUC002N05T116 Rohm None Q5 1 8V MOSFET P CH 8 V 5 3 A SOT 23 SOT 23 Si2329DS Vishay Semiconductor None R1 R25 R30 R54 R60 R64 R72 R73 R75 R76 R78 R80 R90 R93 R94...

Страница 16: ...llow Multipurpose Testpoint 5014 Keystone TP4 TP5 2 Test Point Multipurpose White TH White Multipurpose Testpoint 5012 Keystone TP6 1 Test Point Multipurpose Orange TH Orange Multipurpose Testpoint 50...

Страница 17: ...Bus Transceiver with Configurable Voltage Level Shifting and Three State Outputs DW0024A SOIC 24 DW0024A SN74LVC8T245DWR Texas Instruments Texas Instruments U10 1 150 mA 6 5 V 1 uA IQ Voltage Regulato...

Страница 18: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Страница 19: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Страница 20: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Страница 21: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Страница 22: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Страница 23: ...e resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reprod...

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