Texas Instruments TL16C750EEVM, Руководство пользователя

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Introduction
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2 SLLU317 – January 2020
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Copyright © 2020, Texas Instruments Incorporated
TL16C750EEVM User's Guide
1 Introduction
1.1 Features
• 8x sampling mode for 2x Baud rate support
• Fractional Baud rate support
• 128 Byte FIFO depth
• 5V processor to 3.3V DUT level translation
1.2 Description
This document will cover how to set up the TL16C750EEVM for evaluation.
2 5 V Processor to 3.3 V V
CC
on TL16C750E
The below sections describes how to set up the EVM when using a 5 V digital logic processor to interface
with the TL16C750E used at a 3.3 V logic.
2.1 Using the 5 V to 3.3 V level shifters
To set up and use the EVM with 5 V to 3.3 V level shifting feature, a few adjustments need to be made in
terms of the jumper connections. Shunts should be applied to J9, J31 position 1 and 2, J30 position 2 and
3, J29 position 2 and 3, J24, and J19. An example highlighting this set up is seen in
Figure 1 .
Figure 1. High to low shunt image