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8.

Limitations on Damages and Liability:

8.1

General Limitations

. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,

INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR
REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,
OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF
USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI
MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS
OCCURRED.

8.2

Specific Limitations.

IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED

HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN
CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR
EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE
CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.

9.

Return Policy.

Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)

will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.

10.

Governing Law:

These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,

without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Copyright © 2019, Texas Instruments Incorporated

Содержание TL16C750EEVM

Страница 1: ...EVM with the DUT at 3 3 V or lower 6 6 Loopback mode 7 7 Mode Select 9 8 Reset 10 9 Silkscreen Errors on EVM 10 10 Board Layout 11 11 Schematic and Bill of Materials 12 List of Figures 1 High to low s...

Страница 2: ...EVM for evaluation 2 5 V Processor to 3 3 V VCC on TL16C750E The below sections describes how to set up the EVM when using a 5 V digital logic processor to interface with the TL16C750E used at a 3 3 V...

Страница 3: ...slation Header denoted as J2 allows for the bidirectional data pins D0 D7 to be accessed The 5 V input pins RESET A0 A1 A2 CS IOW and IOR can be accessed at J22 The INT TXRDY and RXRDY lines each have...

Страница 4: ...he expected voltage on the input power J26 is 5 V as this is a common processor voltage range a larger voltage should not be used The input voltage can be lower depending on VDO of the LDO this is out...

Страница 5: ...oted on the EVM as U10 For the 3 3 V regulator to be selected to provide power to the TL16C750E and onboard level shifters J29 must be configured such that position 2 and position 3 are shunted togeth...

Страница 6: ...ition 1 and 2 where the board denotes if VUART 3V6 J30 should be shunted from position 2 and 3 where the board denotes if VUART 3V6 Jumpers denoted as J9 J25 J29 J24 and J19 should not have shunts Fig...

Страница 7: ...s INT TXRDY and RXRDY J12 allow access to the bidirectional data pins D0 D7 J14 are for the input pins RESET A0 A1 A2 CS IOW and IOR J18 provides access to the inputs RI CD DSR CTS and RX Finally J13...

Страница 8: ...Loopback mode www ti com 8 SLLU317 January 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated TL16C750EEVM User s Guide Figure 7 Loopback mode...

Страница 9: ...unted or shunted at position 2 and 3 the TL16C750E is in Intel mode This requires lines CS IOW and IOR to be used to read or write from the device If positions 1 and 2 are shunted on J1 Motorola mode...

Страница 10: ...1 and 2 and J14 position 1 and 2 by toggling the logic level Driving the logic level low places the device in reset Alternatively a hardware reset switch is provided and denoted as S1 A reset is obse...

Страница 11: ...w ti com Board Layout 11 SLLU317 January 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated TL16C750EEVM User s Guide 10 Board Layout Figure 10 EVM top Figure 11 EVM bott...

Страница 12: ...0 1 F C3 50V 0 01 F C5 0 R56 0 R53 0 R59 DNP MR RESET MR RESET 30 R41 CD DSR CTS CD DSR CTS CD_5V DSR_5V CTS_5V CD_5V DSR_5V CTS_5V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 J2 D0_5V D1_5V D2_5V D3_5V D4...

Страница 13: ...01uF C22 25V 0 1uF C21 D5 Iout MAX 150mA 1 2 3 J29 3 3V 0 R110 DNP LDO OUT VCC D7 J10 VUART 3 3V 0 R108 SH J29 www ti com Schematic and Bill of Materials 13 SLLU317 January 2020 Submit Documentation F...

Страница 14: ...CAP CERM 0 01 uF 25 V 5 C0G NP0 0603 0603 C0603H103J3GACTU Kemet C23 1 2 2uF CAP CERM 2 2 uF 16 V 10 X5R 0805 0805 EMK212BJ225KG T Taiyo Yuden D1 D4 2 Yellow LED Yellow SMD LED 1 3x0 65x0 8mm LY L29K...

Страница 15: ...MOSFET N CH 50 V 0 2 A SOT 23 SOT 23 RUC002N05T116 Rohm None Q5 1 8V MOSFET P CH 8 V 5 3 A SOT 23 SOT 23 Si2329DS Vishay Semiconductor None R1 R25 R30 R54 R60 R64 R72 R73 R75 R76 R78 R80 R90 R93 R94...

Страница 16: ...llow Multipurpose Testpoint 5014 Keystone TP4 TP5 2 Test Point Multipurpose White TH White Multipurpose Testpoint 5012 Keystone TP6 1 Test Point Multipurpose Orange TH Orange Multipurpose Testpoint 50...

Страница 17: ...Bus Transceiver with Configurable Voltage Level Shifting and Three State Outputs DW0024A SOIC 24 DW0024A SN74LVC8T245DWR Texas Instruments Texas Instruments U10 1 150 mA 6 5 V 1 uA IQ Voltage Regulato...

Страница 18: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Страница 19: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Страница 20: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Страница 21: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Страница 22: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Страница 23: ...e resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reprod...

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