THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
33
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
clamp acquisition time (continued)
For example, consider clamping an incoming video signal that has a black level near 0.3 V to a black level of
1.3 V at the THS1031 input. The voltage Vc required across the input coupling capacitor is thus 1.3 – 0.3 = 1 V.
If a 10 mV or less clamp voltage error Ve will give acceptable system operation, if the source resistance Rin is
20
Ω
and the coupling capacitor C
IN
is 1
µ
F, then the total clamp pulse duration required to reach this error is:
t
ACQ
+
C
IN
R
IN
In
ǒ
Vc
Ve
Ǔ
+
1
m
F
20
W
In
ǒ
1
0.01
Ǔ
= 92
µ
s (approximately)
Note that SW1 does not have to be closed continuously until the desired clamp voltage is achieved. The clamp
level can be acquired over a longer interval by using a series of shorter clamp pulses with total pulse duration
at least equal to the acquisition time calculated using equation 19.
droop
The charge pulses entering or leaving AIN caused by the sample and hold switched capacitor input can charge
or discharge C
IN
, causing the voltage at AIN to drift toward VM (the average of REFTS and REFBS) during the
time between clamp pulses. This effect is called clamp droop and can be seen as a slow change in the ADC
output code when the input signal is a constant dc level. Through careful clamp circuit design, this droop can
be kept below 1 LSB, giving no change in the ADC output between clamp pulses.
The clamp voltage droop is a function of the input current to the THS1031 and the time between clamp pulses,
td
V
DROOP
+
I
IN
C
IN
td (approximately)
Where:
I
IN
+
(V
AIN
– VM)
ń
ǒ
2
R
AIN
Ǔ
+
(V
AIN
– VM)
CS
fclk
ń
2
R
AIN
is the input resistance given by equation 20. Cs is approximately 2.5 pF. Substituting I
IN
into the droop
voltage equation gives
V
DROOP
+
(V
AIN
– VM)
CS
td
ń
(2
C
IN
)
Note that I
IN
has maximum value when V
AIN
is FS or –FS, and so the droop rate is worst then the clamp
level is near either full-scale input voltage. There is no droop when the clamp level equals VM because I
IN
is
zero. Note that the actual voltage droop may be up to 50% more than given by equation 22 when allowing for
temperature variations and device to device processing variations.
For example, with C
IN
= 1
µ
F at f
clk
= 30 MSPS conversion rate in top/bottom mode with REFTS = 2.5 V and
REFBS = 0.5 V, the clamp droop over td = 63.5 ms when V
AIN
= +FS is
V
DROOP
+
(V
AIN
– VM)
CS
fclk
td
ń
(2
C
IN
)
+
(2.5 V – 1.5 V)
2.5 pF
30 MMz
ń
2
+
0.0024 mV
+
1.25 LSB (assuming PGA gain
+
1)
(20)
(21)
(22)
(23)
