GND
C14
1µF
GREG2
DREG2
C15
0.1µF
IRQ2
PVDD2
GND
0.01uF
C45
OUT2-
CONTROL
IRQ2
ASI1/ASI2
SDOUT1
SDOUT2-2
SDOUT1
SDOUT2-2
OUT2+
GND
GND
GND
1.8V
GND
GND
GND
VBAT2
PVDD2
GND
GND
GND
GND
GND
GND
SD
IOVDD
CONTROL
SD
SDIN1
SCL_SEL2
SDA_MOSI
SPII2C_MISO
ADDR_SPICLK2
SPII2C_MISO
VBAT
SDOUT2-1
SBCLK1
FSYNC
SDIN1
ASI2
ASI1
SDOUT2-1
C1
0.1µF
J1
VBAT2
SW2
1uH
L1
J4
VDD2
4.7uF
C8
0.01uF
C7
IOVDD2
VDD2
J5
IOVDD2
C10
1µF
0.01uF
C9
1
2
3
4
J9
PDM2
PCMCK2
PDMD2
ADDR_SPICLK2
SDA_MOSI
SCL_SEL2
PVDD2
TP1
0
R5
0
R6
VSENSE2-
J3
OUT2
OUT-2P
OUT-2N
0
R3
0
R4
0
R20
0
R21
C49
1µF
C5
C6
C50
1µF
0
R24
C51
1µF
0
R2
SBCLK1
FSYNC
Address = 0x9A
GPIO2
OUT2+
OUT2-
GND
GND
VSNS_N2
VSNS_P2
OUT2+
OUT2-
DF2SE
AUX Connector
OUT2+
OUT2-
OUT2+
OUT2-
GND
SNUBBER
OUT2+
OUT2-
J6
OUT2
25V
C12
10µF
25V
C13
10µF
25V
C3
10µF
25V
C2
10µF
I2C/SPI
SBCLK1
16V
1µF
C11
PDMCK
A1
SW
F1
B2
SBCK1
B3
FSYNC
SDIN1
C2
B4
SCL_SEL
B5
SDA_MOSI
C3
SPII2C_MISO
SD
B1
VBST
G2
D1
VBAT
VDD
C6
PVDD
G4
VBAT
D2
C4
ADDR_SPICLK
D4
GREG
SW
F2
SW
F3
G1
VBST
VBST
G3
G5
PVDD
PVDD
G6
C1
SDOUT1
GPIO
D6
DREG
B6
OUT_P
F5
F6
OUT_N
D5
VSNS_P
D3
VSNS_N
GNDB
E1
IRQ
C5
GNDB
E2
GNDB
E3
GNDD
E4
GNDP
E5
GNDD
F4
GNDP
E6
A2
PDMD
A5
SBCLK2
SDOUT2
A3
SDIN2
A4
IOVDD
A6
U2
TAS2563YBG
EVM Schematics
13
SLAU800 – January 2019
Copyright © 2019, Texas Instruments Incorporated
TAS2563YBGEVM-DC Evaluation module
Figure 13. Channel 2