IRQ1
CONTROL
I2C
SD
SCL
SDA
VBAT
VBAT
GND
1.8V
GND
DF2SE
<
>
>
>
SD
IRQ1
SCL
SDA
FSYNC
SBCLK1
>
<
>
SDIN1
<
<
>
>
>
>
GND
VSENSE2-
1.8V
VSENSE1-
10.0k
R7
>
IRQ2
IRQ1
0
R8
1
2
3
4
J8
GPIO SEL
GPIO2
GPIO1
GND
GND
GND
TP2
GND
TP3
GND
TP4
GND
GND
TP5
GND
3.3V
GND
SCL
SDA
GND
3
GND
5
VCC
U4B
LVC1G125
GND
4
1
2
U4A
LVC1G125
GND
GND
C4
0.1µF
GND
0.1µF
C16
1
3
5
4
6
2
7
9
10
8
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
J2
Power/Analog
1
3
5
4
6
2
7
9
10
8
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
J7
MOSI
ASI/I2C/CONTROL
SPI
MISO
SCL
R13
10.0k
IOVDD
IOVDD
SS0
F
S
S
D
Y
I
N
N1
C
ASI1
SS1
MISO
MOSI
SS0
SS1
GPIO
SS0
GND
3
GND
B
4
OE
1
A
2
5
VCC
U17
CBTLV1G125
GND
3
ADDR_SPICLK1
B
4
OE
1
A
2
5
VCC
U15
1
CBTLV1G125
2
3
J18
SPI
I2C
I2C-SPI SEL
3.3V
GND
2
4
U16A
5
VCC
SN74LVC1G14DCKR
GND
3
NC
1
U16B
SN74LVC1G14DCKR
I2C-EN
SPI-EN
3.3V
GND
I2C-EN
GND
3
SPII2C_MISO
B
4
OE
1
A
2
5
VCC
U8
3
GND
CBTLV1G125
B
4
OE
1
A
2
5
VCC
U7
CBTLV1G125
GND
I2C
I2C
SPI
SPI
MISO
SDA
3
GND
SDA_MOSI
B
4
OE
1
A
2
5
VCC
U6
CBTLV1G125
IOVDD
3
GND
B
4
OE
1
A
2
5
VCC
U5
CBTLV1G125
I2C
SPI
MOSI
GND
3
B
4
OE
1
A
2
5
VCC
U14
GND
3
CBTLV1G125
B
4
OE
1
A
2
5
VCC
U13
I2C
CBTLV1G125
SPI
SCL
SS1
GND
3
B
4
OE
1
A
2
5
VCC
U12
CBTLV1G125
GND
3
ADDR_SPICLK2
B
4
OE
1
A
2
5
VCC
U11
CBTLV1G125
I2C
SPI
3
GND
B
4
OE
1
A
2
5
VCC
U10
3
GND
CBTLV1G125
B
4
OE
1
A
2
5
VCC
U9
I2C
CBTLV1G125
SPI
IOVDD
GND
1
2
3
4
5
6
7
8
J19
ADDR1
10.0k
R16
10.0k
R17
IOVDD
GND
1
2
3
4
5
6
7
8
J17
ADDR2
10.0k
R14
10.0k
R15
CH2
CH2/1
CH1
SCL_SEL2
SCL_SEL1
GND
0.1µF
C43
3.3V
GND
0.1µF
C31
IOVDD
GND
0.1µF
C32
IOVDD
GND
0.1µF
C33
IOVDD
GND
0.1µF
C34
IOVDD
GND
0.1µF
C35
IOVDD
GND
0.1µF
C36
IOVDD
GND
0.1µF
C37
IOVDD
GND
0.1µF
C38
IOVDD
GND
0.1µF
C39
IOVDD
GND
0.1µF
C40
IOVDD
GND
0.1µF
C41
IOVDD
GND
0.1µF
C42
IOVDD
IOVDD
IOVDD
J16
WP
10.0k
R1
>
SPICLK
SPICLK
GPIO
SPICLK
SPICLK
I2C-EN
I2C-EN
I2C-EN
I2C-EN
I2C-EN
SPI-EN
SPI-EN
SPI-EN
SPI-EN
SPI-EN
SPI-EN
I2C Mode Address Selection
I2C Mode Address Selection
0x9E
0x9C
0x9A
0x98*
SDOUT1
SDOUT1
S
S
D
D
O
O
U
U
T
T
2
2
-2
-1
ASI2
<
<
SDOUT2-1
SDOUT2-2
IOVDD
IOVDD
IOVDD
100k
R25
GND
SBCLK1
0x9E
0x9C
0x9A*
0x98
*= Default Address
*= Default Address
5.6V
D1
VBAT
Over Voltage
Protection
GND
A0
1
2
A1
3
A2
4
VSS
5
SDA
6
SCL
WP
7
8
VCC
U3
24FC512-I/ST
EVM Schematics
11
SLAU800 – January 2019
Copyright © 2019, Texas Instruments Incorporated
TAS2563YBGEVM-DC Evaluation module
7
EVM Schematics
Figure 11. Mother Board Connections