Texas Instruments SLAU039, Руководство пользователя

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DSK+ Mode
B-2
B.1 DSK+ Mode
Address bits 0, 14, and 15 are decoded in conjunction with the I/O space select
and the write enable from the C542 on the DSK+. Signals on the data bus are
latched on the rising edge of the
iostrobe signal if a valid write address has
been decoded. Bits 14 and 15 are decoded so as to leave 48 k words of contig-
uous I/O address space free for other hardware that the user might wish to in-
terface to the system. Bit 0 selects one of two control registers implemented
with D latches within the 22V10 device. The first register is used to control the
device reset and
powerdown inputs for both codecs on each board and to con-
trol the powerdown signal to the TLC320AC01 codec on the DSK+ board. The
second register just controls the FC signal. This is to simplify programming of
interleaved secondary communications when the DAC is in 16 bit mode. When
two AD50-EVM boards are used a jumper must be fitted to the primary/sec-
ondary header of one of the boards. The board with the jumper becomes the
secondary one and has channels 3 and 4.
The 22V10 must have a propagation delay of 25 ns or less, assuming that one
or more I/O wait states are programmed in the TMS320C542. Zero wait state
operation would have negligible benefit and would need a much faster and
more costly device.
The AD50s are reset either when the DSK+ is reset or when a 0 is programmed
into bit 0 of address 0. Reset must be held low for at least 6 master clock cycles.
The default configuration at reset is for all the AD50s to be powered down and
for the AC01 on the DSK+ to be operating normally. This means that DSK+ will
continue to operate normally until the 22V10 is programmed for AD50 opera-
tion.
B.2 Stand-Alone Mode
In stand-alone mode all the logic except that used to link the serial interface
is 3-stated. This allows maximum flexibility to control the AD50s via the
CONTROL and SERIAL cable headers.
Table B–1. AD50-EVM Registers
I/O
Address Bits 15–4 Bit 3 Bit 2 Bit 1 Bit 0 Function
0 X X X X 0 Hold AD50 in reset
X X X X 1 Release AD50 from reset
X 0 0 0 X AC01 on DSK+ active
X 0 0 1 X 1 AD50 active
X 0 1 0 X 2 AD50s active
X 0 1 1 X 3 AD50s active
X 1 0 0 0 4 AD50s active
1
X X X X 0 FC pin low
X X X X 1 FC pin high