Texas Instruments SLAU039, Руководство пользователя

Страница: 29 / 66

Programming the AD50 Registers
3-3
Setting Up the AD50-EVM
an oscilloscope for debugging purposes. Then the ’C542 serial port is initial-
ized to 16-bit mode with external frame sync pulses. The AD50 is then taken
out of reset by writing 3 to I/O address 0. The AD50 starts sending frame sync
pulses and a serial clock signal to the ’C542, which responds by transmitting
data from the serial port. This data consists of a list of alternating primary and
secondary transmissions. The primary transmissions are dummy words with
bit 0 set to 1 to request the interleaved secondary transmissions. Each sec-
ondary transmission is a 16-bit word containing commands to initialize the four
control registers of the AD50.
For each secondary transmission, bits 12-8 encode the binary address of the
register to be accessed, bit 13 specifies a read or write access and bits 7–0
contain the data to be written for write operations.
3.4 Programming the AD50 Registers
Register 0 is a dummy register, equivalent in principle to a NOP instruction.
Writing to it does nothing. It is needed so that when several AD50s are cas-
caded it is possible to modify the control registers of one device without dis-
turbing the others.
Register 1 controls reset and power-down status, input selection, monitor am-
plifier signal source and gain, digital loop back test mode and 15 or 16 bit DAC
mode. Once 16 bit mode has been selected, it is not possible to request further
secondary communications by setting bit 0 of a serial port data word. However,
the AD50-EVM provides a means for driving the FC pin of the AD50 chip by
writing to bit 0 of I/O address 1. The value written is applied to the FC pin, and
a 1 initiates a hardware secondary communication request. FC is sampled by
the AD50 on the rising edge of frame sync.
Register 2 allows control of the flag bit, reading of the decimator overflow flag,
selection of 15 or 16 bit ADC mode and control of the analog loop back test
mode.
Register 3 is used to select the number of cascaded AD50 devices (up to a
maximum of 1 master and 3 slaves) and to control the time between commu-
nications from each device. It is important that register 3 is only programmed
after the sampling frequency has been set. It is convenient to program every-
thing common to all the devices prior to setting register 3. Thereafter, when
secondary communications are requested, each device takes part in turn and
must either be programmed individually or a NOP instruction sent to register
0.
Register 4 controls the analog input and output gains and the sampling
frequency.
It is only necessary to reprogram those registers that have unsuitable default
values. If none of the AD50 registers are programmed, the system will default
to a sampling frequency of 10 kHz for a MCLK frequency of 10.24 MHz. If I/O
address 0 is not programmed as described above, the system will default to
using the AC01 ADC and DAC as normal.