PCM5122/42EVM-U
Table 1. PCM5122/42EVM-U Headers, Test Points, Jumpers, and Switches (continued)
Connectors/Switch/Jumper/Test Point
Description
J5
Coaxial S/PDIF input
J6
BNC external MCLK input
Switches
SW1
EVM reset
SW2
Select EVM application
SW3
MCLK select
LEDs
D2
RX lock
D3
SRC ready
2.5
Clock Circuitry
SW3 allows for MCLK selection from multiple sources. The PCM5122/42EVM-U contains an external BNC
jack, J6, as well as one programmed oscillator that provides a clock frequency of 24.576 MHz. The
TAS1020B also provides a MCLK output; by default, this clock is used as the master clock for the
PCM5122/42EVM-U. Depending on the application requirements, the SRC4392 is also able to derive a
received clock output (RCKO) output based on the input clock frequency, and this derived clock output
can be used as the MCLK input for the PCM5122/42 as well. This option is enabled by setting a shunt in
position 1-2 (RXCKO) on the 3-pin jumper W5. If W5 has a shunt in position 2-3, then setting SW3
determines which MCLK source is used, as summarized in
Table 2. SW3 Clock Selection
Setting
A
B
C
Onboard MCLK from TAS1020B
Low
Low
Low
External MCLK 3.3-V BNC Input
High
Low
Low
24.576-MHz MCLK from PLL Y3
High
High
High
2.5.1
MCLK Source Matching
The SRC4392 is equipped with two audio serial data ports, each of which generates BCLK and LRCLK
signals. When the SRC4392 receives an S/PDIF input, it automatically derives the MCLK of the input,
which is sent to the RXCKO pin. Dividers are used to send the generated BLCK and LRCLK from the
audio ports (if they are in master mode). For certain use cases, the SRC4392 is set up so that these ports
are used. When routing through the audio serial ports on the SRC4392, it is important to use RXCKO as
the master clock source for the PCM5122/42. In order to ensure proper operation, the master clock source
must be synchronized to the bit and word clock supplied to the PCM5122/42. Therefore, the master clock
source for the PCM5122/42 must also be replicated from the digital input source, which is why RXCKO
must be chosen. If the master clock source for the PCM5122/42 is the onboard MCLK from the TAS1020B
USB controller, for example, then there is potential for synchronization mismatch between the master
clock supplied to the PCM5122/42 and the bit and word clocks being supplied to the PCM5122/42. For
use cases routing through the SRC4392 audio serial ports, look to jumper W5 for selecting RXCKO as the
master clock source, as opposed to one of the options chosen by adjusting SW3. The
has additional routing information.
The PCM5122/42 devices contain an internal PLL and BCLK reference, so that the MCLK can be
generated internally. When using external I
2
S input directly into the W3 jumper, a MCLK can be derived
form the BCLK input. Refer to the
for more details.
6
PCM5122/42EVM-U
SLAU444 – May 2012
Copyright © 2012, Texas Instruments Incorporated
