Texas Instruments MSP430F6723, Руководство пользователя

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transfer sequence is missed, all the following bytes are missed as well. All eUSCI_A
modes (UART, SPI, and IrDA) and all eUSCI_B modes (SPI and I2C) are affected.
Workaround 1) Use Interrupt Service Routines to transfer data to and from the eUSCI_A or eUSCI_B.
OR
2) When using DMA channel 0 for transferring data to and from the eUSCI_A or
eUSCI_B, use DMA channel 2 (lower priority than DMA channel 0) to read the same
register of the eUSCI_A or eUSCI_B that DMA channel 0 is working with. Use the same
USCI IFG (e.g. UCA0RXIFG) as trigger source for these both DMA channels.
DMA10
DMA Module
Category
Functional
Function DMA access may cause invalid module operation
Description The peripheral modules MPY, CRC, USB, RF1A and FRAM controller in manual mode
can stall the CPU by issuing wait states while in operation. If a DMA access to the
module occurs while that module is issuing a wait state, the module may exhibit undefined
behavior.
Workaround Ensure that DMA accesses to the affected modules occur only when the modules are
not in operation. For example with the MPY module, ensure that the MPY operation is
completed before triggering a DMA access to the MPY module.
EEM8
EEM Module
Category
Debug
Function Debugger stops responding when using the DMA
Description In repeated transfer mode, the DMA automatically reloads the size counter (DMAxSZ)
once a transfer is complete and immediately continues to execute the next transfer unless
the DMA Enable bit (DMAEN) has been previously cleared. In burst-block transfer mode,
DMA block transfers are interleaved with CPU activity 80/20% - of ten CPU cycles, eight
are allocated to a block transfer and two are allocated for the CPU.
Because the JTAG system must wait for the CPU bus to be clear to halt the device, it can
only do so when two conditions are met:
- Three clock cycles after any DMA transfer, the DMA is no longer requesting the bus.
and
- The CPU is not requesting the bus.
Therefore, if the DMA is configured to operate in the repeat burst-block transfer mode,
and a breakpoint is set between the line of code that triggers the DMA transfers and the
line that clears the DMAEN bit, the DMA always requests the bus and the JTAG system
never gains control of the device.
Workaround When operating the DMA in repeat burst-block transfer mode, set breakpoint(s) only when
the DMA transfers are not active (before the start or after the end of the DMA transfers).
EEM17
EEM Module
Category
Debug
Function Wrong Breakpoint halt after executing Flash Erase/Write instructions
www.ti.com Advisory Descriptions
SLAZ340AF – OCTOBER 2012 – REVISED MAY 2021
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MSP430F6723 Microcontroller 13
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