Texas Instruments MSP430CG4616IPZ, Руководство пользователя

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MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
57
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit DAC, reference input specifications
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Ve
Reference input
DAC12IR=0 (see Notes 1 and 2)
2 2 V/3 V
AV
CC
/3 AV
CC
+0.2
V Ve
REF+
Reference input
voltage range
DAC12IR=1 (see Notes 3 and 4)
2.2 V/3 V
AVcc AVcc+0.2
V
DAC12_0 IR=DAC12_1 IR =0 20 M
Ω
DAC12_0 IR=1, DAC12_1 IR = 0
40 48 56
Ri
(VREF+)
, Reference input DAC12_0 IR=0, DAC12_1 IR = 1
2 2 V/3 V
40 48 56
(VREF+)
,
Ri
(VeREF+)
p
resistance
DAC12_0 IR=DAC12_1 IR =1,
DAC12_0 SREFx = DAC12_1 SREFx
(see Note 5)
2.2 V/3 V
20 24 28
k
Ω
NOTES: 1. For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AV
CC
).
2. The maximum voltage applied at reference input voltage terminal Ve
REF+
= [AV
CC
− V
E(O)
] / [3*(1 + E
G
)].
3. For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AV
CC
).
4. The maximum voltage applied at reference input voltage terminal Ve
REF+
= [AV
CC
− V
E(O)
] / (1 + E
G
).
5. When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
12-bit DAC, dynamic specifications; V
ref
= V
CC
, DAC12IR = 1 (see Figure 30 and Figure 31)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
DAC12
DAC12_xDAT = 800h,
DAC12AMPx = 0
→
{2, 3, 4} 60 120
t
ON
DAC12
on time
DAC12_xDAT = 800h,
Error
V(O)
<
±
0.5 LSB
DAC12AMPx = 0
→
{5, 6}
2.2 V/3 V
15 30
μ
s t
ON
on-time
Error
V(O)
<
±
0.5 LSB
(see Note 1,Figure 30)
DAC12AMPx = 0
→
7
2.2 V/3 V
6 12
μ
s
Settling time DAC12 xDAT
DAC12AMPx = 2 100 200
t
S(FS)
Settling time,
full scale
DAC12_xDAT =
80h
→
F7Fh
→
80h
DAC12AMPx = 3,5
2.2 V/3 V
40 80
μ
s t
S(FS)
full-scale 80h
→
F7Fh
→
80h
DAC12AMPx = 4,6,7
2.2 V/3 V
15 30
μ
s
Settling time
DAC12_xDAT =
DAC12AMPx = 2 5
t
S(C-C)
Settling time,
code to code
DAC12_xDAT =
3F8h
→
408h
→
3F8h
DAC12AMPx = 3,5
2.2 V/3 V
2
μ
s t
S(C-C)
code to code
3F8h
→
408h
→
3F8h
BF8h
→
C08h
→
BF8h
DAC12AMPx = 4,6,7
2.2 V/3 V
1
μ
s
DAC12_xDAT =
DAC12AMPx = 2 0.05 0.12
SR Slew rate
DAC12_xDAT =
80h
→
F7Fh
→
80h DAC12AMPx = 3,5
2.2 V/3 V
0.35 0.7
V/
μ
s SR Slew rate
80h
→
F7Fh
→
80h
(see Note 2)
DAC12AMPx = 4,6,7
2.2 V/3 V
1.5 2.7
V/
μ
s
DAC12 xDAT
DAC12AMPx = 2 600
Glitch energy, full-scale
DAC12_xDAT =
80h
→
F7Fh
→
80h
DAC12AMPx = 3,5
2.2 V/3 V
150
nV-s Glitch energy, full scale
80h
→
F7Fh
→
80h
DAC12AMPx = 4,6,7
2.2 V/3 V
30
nV s
NOTES: 1. R
Load
and C
Load
connected to AV
SS
(not AV
CC
/2) in Figure 30.
2. Slew rate applies to output voltage steps >= 200mV.
RLoad
AVCC
CLoad = 100pF
2
DAC Output
RO/P(DAC12.x)
ILoad
Conversion 1 Conversion 2
VOUT
Conversion 3
Glitch
Energy
+/− 1/2 LSB
+/− 1/2 LSB
tsettleLH tsettleHL
= 3 k
Ω
Figure 30. Settling Time and Glitch Energy Testing