( H_DDR_RET_1V1), must be set before entering RETENTION. In this example GPIO4 on the TPS65941213 is
used to wake the device from RETENTION to ACTIVE.
Write 0x48:0x85:0x80:0x7F // I2C_7 is high
Write 0x4C:0x85:0x80:0x7F
Write 0x48:0x34:0xC0;0x3F // Set GPIO4 to WKUP1 (goes to ACTIVE state)
Write 0x48:0x64:0x08:0xF7 // clear interrupt of gpio4, write to clear
Write 0x48:0x4F:0x00:0xF7 // unmask interrupt for GPIO4 falling edge
Write 0x4C:0x3D:0x08:0xF7 // set PMICB:GPIO4, H_DDR_RET_1V1
Write 0x48:0x86:0x00:0xFC // trigger the TO_RETENTION power sequence
After the GPIO4 has gone low and the PMICs have returned to the ACTIVE state
Write 0x48:0x86:0x03:0xFC // Set NSLEEPx bits for ACTIVE state
Write 0x48:0x64:0x08:0xF7 // clear interrupt of gpio4
Write 0x4C:0x3D:0x00:0xF7 // clear PMICB:GPIO4, DDR_RET
In this example the TPS65941213 RTC Timer is used to wake the device from RETENTION to ACTIVE.
Write 0x48:0x85:0x80:0x7F // I2C_7 is high
Write 0x4C:0x85:0x80:0x7F
Write 0x48:0xC3:0x01;0xFE // Enable Crystal
Write 0x48:0xC5:0x05:0xF8 // minute timer, enable TIMER interrupts
Write 0x48:0xC2:0x01:0xFE // start timer, if the timer values are non-zero clear before starting
Write 0x4C:0x3D:0x08:0xF7 // set PMICB:GPIO4, H_DDR_RET_1V1
Write 0x48:0x86:0x00:0xFC // trigger the TO_RETENTION power sequence
After the RTC Timer interrupt has occurred and the PMICs have returned to the ACTIVE state
Write 0x48:0x86:0x03:0xFC // Set NSLEEPx bits for ACTIVE state
Write 0x48:0xC5:0x00:0xFB // disable timer interrupt, clear bit 2
Write 0x48:0xC4:0x00:0xDF // clear timer interrupt, clear bit 5
Write 0x4C:0x3D:0x00:0xF7 // clear PMICB:GPIO4, DDR_RET
7.2 Entering and Exiting Standby
STANDBY can be entered from ACTIVE, MCU ONLY, or the RETENTION states. In order to stay in the mission
state of STANDBY and not enter the hardware state LP_STANDBY the LP_STANDBY_SEL bit must be cleared.
Similar to the RETENTION state the STANDBY state turns off all regulators which power the MCU. Therefore, it
is required to select the state, MCU ONLY or ACTIVE, that the STANDBY state returns to.
When the ENABLE pin goes low, the TO_STANDBY sequence is triggered. When the ENABLE pin goes high
again, the destination state is dependent upon the STARTUP_DEST bits. The TO_STANDBY sequence is also
triggered by the I2C_0 trigger. When triggered from I2C_0 the PMIC can be triggered to return to either the
ACTIVE or MCU ONLY states by GPIO4, GPIO10, or and RTC timer or alarm. In this example, I2C_0 trigger is
used to enter the STANDBY state and the GPIO4 is used to enter the ACTIVE state.
Write 0x48:0xC3:0x00:0xF7 // LP_STANDBY_SEL=0
Write 0x48:0x7D:0xC0:0x3F // Mask NSLEEP bits
Write 0x48:0x34:0xC0;0x3F // Set GPIO4 to WKUP1 (goes to ACTIVE state)
Write 0x48:0x64:0x08:0xF7 // clear interrupt of GPIO4
Write 0x48:0x4F:0x00:0xF7 // unmask interrupt for GPIO4 falling edge
Write 0x48:0x85:0x01:0xFE // set I2C_0 trigger, trigger TO_STANDBY sequence
After the GPIO4 has gone low and the PMICs have returned to the ACTIVE state
Write 0x48:0x7D:0x00:0x3F // unmask NSLEEP bits
Write 0x48:0x86:0x03:0xFC // Set NSLEEPx bits for ACTIVE state
Write 0x48:0x64:0x08:0xF7 // clear interrupt of GPIO4
7.3 Entering and Existing LP_STANDBY
Entering the LP_STANDBY hardware state is the same as entering STANDBY. Exiting LP_STANDBY is
different and requires different initializations before entering LP_STANDBY. Also, when the PMICs return from
LP_STANDBY the PFSM triggers are gated by the ENABLE_INT while in STANDBY the triggers were gated by
the GPIO interrupt.
Write 0x48:0xC3:0x08:0xF7 // LP_STANDBY_SEL=1
Write 0x48:0x7D:0xC0:0x3F // Mask NSLEEP bits
Write 0x48:0x34:0xC0;0x3F // Set GPIO4 to WKUP1 (goes to ACTIVE state)
Write 0x48:0xC3:0x60;0x9F // Set the STARTUP_DEST=ACTIVE
Write 0x48:0x64:0x08:0xF7 // clear interrupt of GPIO4
Application Examples
SLVUC99 – JANUARY 2022
Optimized Dual TPS6594-Q1 PMIC User Guide for Jacinto
™
7 DRA829 or
TDA4VM Automotive PDN-0C
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Copyright © 2022 Texas Instruments Incorporated
