Texas Instruments FPD23DAEVM, Руководство пользователя

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Chapter 3
SNLU144 – may 2013
Evaluation Hardware Overview
FPD23DAEVM includes circuits and interfaces facilitating the full control over the devices present on the
board.
3.1 Power
FPD23DAEVM can be powered up by 6V(min) to 12V(max) DC supply as detailed in Figure 2-1 and
Figure 2-2 . Apply power to only ONE of these ports: J1 or J6.
Table 3-1. Power
Reference Description and Default settings
12V power port
J1
Do not apply more than 12V and less than 6V DCsupply to this port.
12V power jack
J6
Do not apply more than 12V and less than 6V DCsupply to this port.
3.3V power port
J5 This port can be used to power up the Deserializer board to which the adapter is connected. It can
source up to 400mA of current.
3.2 Video Data Input
As mentioned earlier, there two input options available.
NOTE: To ensure electrical signal compatibility,
1. Board is by default configured for LVCMOS threshold of V
IH(min)
= 2.31V and
V
IL(max)
= 0.99V for the PanelBus Transmitter, TFP410. This allows using this
board with deserializer VDDIO = 3.3V.
2. To work with low signal swings (with deserializer VDDIO = 1.8V), change R7 to
40k Ω and R8 to 15k Ω . This hardware change corresponds to V
IH(min)
= 1.1V and
V
IL(max)
= 0.7V.
3.2.1 FPD-Link Video Data Input
Header J3 (mounted on bottom side) accepts a 20-pin IDC or similar 0.1" spaced male header. Connect
the clock and 4 FPD-Link (LVDS) data pairs to this header as marked on the silk screen. 100
Ω differential
termination is provided on the board near DS90CF386 (U4) device pins.
Figure 3-1. FPD-Link Input header: J3
6 Evaluation Hardware Overview SNLU144 – may 2013
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