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Schematic and PCB Layout
21
SBOU191 – July 2017
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Copyright © 2017, Texas Instruments Incorporated
DIYAMP-SOT23-EVM
The PCB layout of the top layer of the non-inverting comparator circuit configuration is displayed in
Figure 34
.
Figure 34. Non-inverting Comparator Top Layer
The PCB layout of the top layer of the non-inverting comparator circuit configuration is displayed in
Figure 35
.
Figure 35. Non-Inverting Comparator Bottom Layer
3.11 R
iso
With Dual Feedback
Figure 36
shows the schematic for the R
iso
with dual-feedback circuit configuration.
Figure 36. R
iso
with Dual-Feedback Schematic
The dc gain of the R
iso
with dual-feedback circuit configuration can be calculated using
Equation 24
.
(24)