(
)
(
)
th
2
1
l
th
V
V
R
R
V
V
+
+
=
-
(
)
h
th
1
2
th
V
V
R
R
V
-
=
4
th
ref
3
4
R
V
V
R
R
æ
ö
= ç
÷
+
è
ø
+
±
R1
R2
R4
VOUT
VIN
V+
C1
VREF
R3
Schematic and PCB Layout
www.ti.com
20
SBOU191 – July 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DIYAMP-SOT23-EVM
The PCB layout of the bottom layer of the inverting comparator circuit configuration is displayed in
Figure 32
.
Figure 32. Inverting Comparator Bottom Layer
3.10 Non-Inverting Comparator
Figure 33
shows the schematic for the non-inverting comparator circuit configuration.
Figure 33. Non-Inverting Comparator Schematic
It is important to note that this circuit layout is meant for SOT23 package op amp or push-pull output type
comparators. This configuration uses a voltage divider R3 and R4 to set up the threshold voltage. The
comparator will compare the input signal (Vin) to the threshold voltage (Vth).
(21)
The comparator input signal is applied to the non-inverting input, so the output will have a non-inverted
polarity. When Vin > Vth, the output will drive to the positive supply (V+ or logic high). When Vin < Vth, the
output will drive to the negative supply (GND or logic low).
R2 can be populated to implement hysteresis which uses two different threshold voltages to avoid the
multiple transitions. The input signal must exceed the upper threshold (VH) to transition high or below the
lower threshold (VL) to transition low.
Equation 22
and
Equation 23
will calculate the value of R1 and R2
for the two desired thresholds.
(22)
(23)