Texas Instruments DAC5686 EVM, Руководство пользователя

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4 Circuit Description
4.1 Input Clocks
4.2 Input Data
Circuit Description
Table 1. DAC5686 EVM Parts List (continued)
Bill Of Material For DAC5686
Value QTY Part Number Vendor Ref Des Not Installed
Black banana jacks 2 ST-351B Allied J9, J10
DAC5686PZP 1 DAC5686IPZP TI U1
SN74LVC1G125DBVR 1 SN74LVC1G125D TI U5
BVR
SN74HC241PW 1 SN74HC241PW TI U4
Transformer 2 T4-1-KK8 Mini-circuit T1, T2
Transformer 2 TCM4-1W Mini-circuit T3, T4
DB25F-RA 1 745536-2 AMP J1
Mounting screws 2 J1
Nuts 2 J1
Switch 1 EVQ-PJX04M Panasonic S1
This chapter describes the circuit functions of the DAC5686 EVM.
The initial configuration of this EVM provides transformer-coupled differential clocks from single-ended
input sources. A 300-mV
P-P
, 0-V offset, 50% duty cycle external square wave is applied to SMA connector
J3 to be used as the data clock input. The signal is converted to a differential clock by transformer T3 and
provides the CLK1 and CLK1C inputs to the DAC5686 device. This input represents a 50-
Ω
load to the
source. In order to preserve the specified performance of the DAC5686 converter, the clock source should
feature very low jitter. Using a clock with a 50% duty cycle gives optimum dynamic performance.
A 300 mV
PP
, 0-V offset, 50% duty cycle external square wave is applied to SMA connector J4 to be used
as the DAC sample clock. The signal is converted to a differential clock by transformer T4 and provides
the CLK2 and CLK2C inputs to the DAC5686 device. This input represents a 50-
Ω
load to the source. In
order to preserve the specified performance of the DAC5686 converter, the clock source should feature
low jitter. Using a clock with a 50% duty cycle gives optimum dynamic performance.
The DAC5686 EVM can accept 1.8-V or 3.3-V CMOS logic level data inputs through the 34-pin headers
J13 and J14 per
Table 2 and Table 3 . The board provides 50-
Ω
termination option to ground and series
dampening resistors to minimize digital ringing and switching noise.
Table 2. Input Connector J13 (Data A Bus)
Pin Description Pin Description
1 CMOS data bit 15 (MSB) 18 GND
2 GND 19 CMOS data bit 6
3 CMOS data bit 14 20 GND
4 GND 21 CMOS data bit 5
5 CMOS data bit 13 22 GND
6 GND 23 CMOS data bit 4
7 CMOS data bit 12 24 GND
8 GND 25 CMOS data bit 3
9 CMOS data bit 11 26 GND
10 GND 27 CMOS data bit 2
SLWU006E – December 2004 – Revised March 2007 DAC5686 EVM 21
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