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4.3.2
Unbuffered Differential Output
4.3.3
PLL Lock
4.4
Control Inputs
4.4.1
Sleep Mode
4.4.2
Reset
4.4.3
Phase Synchronization
4.4.4
TxENABLE
4.4.5
QFLAG
4.4.6
PLL_ON_OFF
Circuit Description
To provide unbuffered differential outputs, the EVM must be configured as follows: remove R21, R22, T1,
and T2; install R5 (24.9), R10 (24.9), R19 (24.9), R20 (24.9), R24, R27-R30, and R32. With a 20 mA
full-scale output current, this configuration provides a 0.5 V
PP
output.
With the internal PLL enabled (W3 installed between pins 1 and 2), when the PLL is locked to the CLK1
input, PLLOCK is driven high. With the internal PLL disabled, the PLLLOCK is an output clock that can be
used by external devices to clock the input data to the DAC5686. This signal is the CLK2 signal divided
down by the interpolation rate and phase-aligned to allow the user to clock data into the DAC5686 with the
required setup and hold times.
The DAC5686 device has six discrete inputs to control the operation of the device.
The DAC5686 EVM provides a means of placing the DAC5686 device into a power-down mode. This
mode is activated by placing a jumper between pins 5 and 6 on header J15.
The DAC5686 EVM provides a means of resetting the DAC5686 device. Pressing switch S1 or sending
J15 pin 29 low provides an active low reset signal to the DAC5686 device.
The DAC5686 EVM provides a means to phase synchronize the DAC5686 device. Placing an active high
signal on J15 pin 8 (PHSTR) resets the internal NCO accumulator register.
TxENABLE must be high to enable the DAC5686 process data. When low, the DAC5686 device is forced
to a constant dc output at IOUTA and IOTB. When in the interleaved mode and MEM_QFLAG bit is set to
0, TxENABLE syncronizes the data of channels A and B. When TxENABLE goes high, data present at the
next clock rising edge is treated as I data. The next valid data is then treated as Q data and so on.
TxENABLE is controlled by J15 pin 11.
QFLAG is an input used to indicate Q sample data during the interleaved mode when the QFLAG
interleave bit (3) is set in register #9, MEM_QFLAG. When QFLAG is high, input data is treated as Q data,
and when low, data is treated as I data. QFLAG is controlled by J15 pin 14.
PLL_ON_OFF allows the user to disable the PLLLOCK output buffer. When PLL_ON_OFF is high, the
buffer is disabled. When low, the PLLLOCK output signal is present at SMA connector J2.
SLWU006E – December 2004 – Revised March 2007
DAC5686 EVM
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