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21−Mar−2006

DOCUMENTCONTROL #

C7

.1uF

DAC5686

B

1

5

J.

S

E

T

O

N

Y

. D

E

W

O

N

C

K

C6

.1uF

D

A

0

D

A

1

D

A

2

D

A

3

D

A

4

D

A

5

D

A

6

D

A

7

D

A

8

D

A

9

D

A

1

0

D

A

1

1

D

A

1

2

D

A

1

3

D

A

1

4

D

A

1

5

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

DB10

DB11

DB12

DB13

DB14

DB15

CLK2C

CLK2

CLK1C

CLK1

+1.8VD

DB(0..15)

DA(0..15)

C5

.1uF

C4

.1uF

C3

10pF

C2

.1uF

C1

.1uF

C8

.1uF

S

C

L

K

S

D

IO

SCLK

SDIO

C9

.1uF

C10

.1uF

C1

1

.1uF

C14

.01uF

C12

.1uF

C13

.1uF

TXENABLE

T

X

E

N

A

B

L

E

SDENB

S

D

E

N

B

IOVDD

R25

127

C34

15000pF

C33

120pF

R13

49.9

P

H

S

T

R

R4

1K

IOVDD

S1

SW−PB

C16

.1uF

R1

1K

IOVDD

1

3

2

W1

+3.3V

A

C18

.1uF

C17

.1uF

+3.3V

A

+3.3V

A

+1.8VD

+1.8VD

+3.3VPLL

+3.3VCLK

S

L

E

E

P

Q

F

L

A

G

R39

49.9

R12

49.9

SLEEP

QFLAG

C86

.1uF

C85

.1uF

C84

.1uF

C29

.1uF

C15

.1uF

+3.3V

A

R40

49.9

(SH 4)

(SH 4)

(SH 4)

(SH 2)

(SH 2)

(SH 2)

+

C24

10uF

+

C38

10uF

+

C37

10uF

+

C39

10uF

+

C41

10uF

RESET

RESET

(SH 2)

(SH 2)

(SH 2)

R10

100

R33

0

C61

.1uF

R21

100

R5

100

1

2

3

4

5

J18

 SMA

1

2

3

4

5

J5

SMA

+3.3V

A

R29

0

R28

0

(Note 1)

IOUT

A

R23

0

(Note 1)

R24

0

R19

100

R20

100

1

2

3

4

5

J19

SMA

R22

100

C60

.1uF

R31

0

+3.3V

A

1

2

3

4

5

J6

SMA

R30

0

R32

0

(Note 1)

R26

0

(Note 1)

R27

0

(Note 1)

(Note 1)

(Note 1)

(Note 1)

IO

U

T

B

+3.3V

A

+3.3V

A

NOTE 1. DO NOT INST

ALL

1

2

3

4

5

J2

SMA

C25

.1uF

+

C26

10uF

IOVDD

CLK1C

CLK1

CLK2

CLK2C

(SH 3)

(SH 3)

(SH 3)

(SH 3)

PHSTR

(SH 2)

SDO

S

D

O

(SH 4)

4

6

3

2

1

T

2

T4−1−KK81

4

6

3

2

1

T

1

T4−1−KK81

R16

22.1

R17

221

R18

1

10

IOVDD

(Note 1)

R38

22.1

(Note 1)

(Note 1)

(2−3)

(Note 1)

(Note 1)

C59

.1uF

R43

10

OE

1

GND

3

Y

4

VCC

5

A

2

U

5

SN74LVC1G125

P

L

L

_

O

N

_

O

F

F

PLL_ON_OFF

(SH 2)

DVDD

26

DGND

27

SDENB

28

SCLK

29

SDIO

30

SDO

31

DVDD

32

TXENABLE

33

DA15

34

DA14

35

DA13

36

DVDD

37

DGND

38

DA12

39

DA1

1

40

DA10

41

DA9

42

DA8

43

DVDD

44

DGND

45

IOVDD

46

IOGND

47

DA7

48

DA6

49

DA5

50

DA4

51

DA3

52

DA2

53

DA1

54

DA0

55

DVDD

56

DGND

57

CLKGND

58

CLK1

59

CLK1C

60

CLKVDD

61

CLK2

62

CLK2C

63

CLKGND

64

PLLGND

65

LPF

66

PLLVDD

67

DVDD

68

DGND

69

PLLLOCK

70

DB0

71

DB1

72

DB2

73

DB3

74

DB4

75

DB5

76

DB6

77

DB7

78

IOGND

79

IOVDD

80

DGND

81

DVDD

82

DB8

83

DB9

84

DB10

85

DB1

1

86

DB12

87

DGND

88

DVDD

89

DB13

90

DB14

91

DB15

92

DGND

93

PHSTR

94

/RESETB

95

SLEEP

96

TESTMODE

97

QFLAG

98

DGND

99

DVDD

100

AGND

1

AVDD

2

AVDD

3

AGND

4

IOUTB1

5

IOUTB2

6

AGND

7

AVDD

8

AGND

9

AVDD

10

EXTIO

11

AGND

12

BIASJ

13

AVDD

14

EXTLO

15

AVDD

16

AGND

17

AVDD

18

AGND

19

IOUTA2

20

IOUTA1

21

AGND

22

AVDD

23

AVDD

24

AGND

25

U

1

DAC5686

Schematic

Figure 9. Schematic - Page 1

26

DAC5686 EVM

SLWU006E – December 2004 – Revised March 2007

Submit Documentation Feedback

Содержание DAC5686 EVM

Страница 1: ...DAC5686 EVM User s Guide March 2007 Wireless Infrastructure Products SLWU006E...

Страница 2: ...2 SLWU006E December 2004 Revised March 2007 Submit Documentation Feedback...

Страница 3: ...86 EVM Initial Setup Tests 11 2 3 DAC5686 GUI Register Descriptions 13 3 Physical Description 15 3 1 PCB Layout 15 3 2 Parts List 19 4 Circuit Description 21 4 1 Input Clocks 21 4 2 Input Data 21 4 3...

Страница 4: ...ff 12 4 Spectrum with CLK2 320 MHz X4 Interpolation Single Sideband Mode and NCO Frequency 536870912 13 5 Top Layer 1 16 6 Layer 2 Ground Plane 17 7 Layer 3 Power Plane 18 8 Bottom Layer 19 9 Schemati...

Страница 5: ...EVM allows for different clock configurations The user can input a single ended differential ECL PECL or TTL CMOS level signal to be used to generate a single ended or differential clock source See Se...

Страница 6: ...rough RBIAS resistor R1 The DAC5686 output is enabled sleep mode disabled TXENABLE is set high to enable the DAC5686 device to process data Internal PLL disabled Jumper W3 is installed between pins 2...

Страница 7: ...cable to J1 on the EVM and skip steps 2 to 7 2 USB Interface Connect the provided USB to SPI adapter board to the parallel port connector on the EVM and to a spare USB port on the host PC using the s...

Страница 8: ...k and select Install from a list or specific location advanced Click Next 5 Select Search for the best driver in these locations and browse for the folder where the DAC5686 program was installed the d...

Страница 9: ...ing a Microsoft WHQL certified driver Click on Continue Anyway to continue with the installation If Windows XP is configured to ignore file signature warnings no message will appear 7 Windows should t...

Страница 10: ...re is a problem with the communication such as the EVM is not powered on or the parallel port cable is not connected an error message will be displayed instructing the user to correct the problem Once...

Страница 11: ...ovide a CLK2 input and disable the internal PLL W3 between pins 2 and 3 Do not provide parallel input data 2 Power up the EVM with 1 8 V DVDD and 3 3 V AVDD 3 Start the DAC5686_SPI software 4 Turn Ful...

Страница 12: ...TB In the case of CLK2 500 MHz the output spectrum should be similar to Figure 3 with a tone at 125 MHz This tone is being generated by the DAC5686 Fdac 4 Coarse Mixer as with no input data provided t...

Страница 13: ...lation Single Sideband Mode and NCO Frequency 536870912 6 Changing the NCO DDS to 268435456 232 20 320 will now result at an output tone at 20 MHz The following section provides a brief description of...

Страница 14: ...differential clocks are used to input the data to the chip CLK1 CLK1C is used to latch the input data into the chip and CLK2 CLK2C is used as the DAC sample clock NCO When set enables NCO in Single S...

Страница 15: ...error message will be displayed This chapter describes the physical characteristics and PCB layout of the EVM and lists the components used on the module The EVM is constructed on a 4 layer 6 5 inch...

Страница 16: ...www ti com Physical Description Figure 5 Top Layer 1 16 DAC5686 EVM SLWU006E December 2004 Revised March 2007 Submit Documentation Feedback...

Страница 17: ...www ti com Physical Description Figure 6 Layer 2 Ground Plane SLWU006E December 2004 Revised March 2007 DAC5686 EVM 17 Submit Documentation Feedback...

Страница 18: ...www ti com Physical Description Figure 7 Layer 3 Power Plane 18 DAC5686 EVM SLWU006E December 2004 Revised March 2007 Submit Documentation Feedback...

Страница 19: ...ti com 3 2 Parts List Physical Description Figure 8 Bottom Layer Table 1 lists the parts used in constructing the EVM SLWU006E December 2004 Revised March 2007 DAC5686 EVM 19 Submit Documentation Feed...

Страница 20: ...F10R0V Panasonic R3 R15 0 resistor 1 16 W 1 2 ERJ 3GEY0R00V Panasonic R23 R26 R24 R27 R33 49 9 resistor 1 16 W 1 3 ERJ 3EKF49R9V Panasonic R12 R13 R39 R40 127 resistor 1 16 W 1 1 ERJ 3EKF1270V Panason...

Страница 21: ...the clock source should feature very low jitter Using a clock with a 50 duty cycle gives optimum dynamic performance A 300 mVPP 0 V offset 50 duty cycle external square wave is applied to SMA connect...

Страница 22: ...ured to drive a doubly terminated 50 W cable or provide unbuffered differential outputs The factory set configuration of the demonstration board provides the user with single ended output signals at S...

Страница 23: ...pins 5 and 6 on header J15 The DAC5686 EVM provides a means of resetting the DAC5686 device Pressing switch S1 or sending J15 pin 29 low provides an active low reset signal to the DAC5686 device The D...

Страница 24: ...e output current IOUTFS is defined as follows where VEXTIO is the voltage at pin EXTIO This voltage is 1 2 V typical when using the internally provided bandgap reference voltage source The internal re...

Страница 25: ...www ti com 5 Schematic Schematic This chapter contains the DAC5686 EVM schematic diagrams SLWU006E December 2004 Revised March 2007 DAC5686 EVM 25 Submit Documentation Feedback...

Страница 26: ...0 Note 1 Note 1 Note 1 Note 1 IOUTB 3 3VA 3 3VA NOTE 1 DO NOT INSTALL 1 2 3 4 5 J2 SMA C25 1uF C26 10uF IOVDD CLK1C CLK1 CLK2 CLK2C SH 3 SH 3 SH 3 SH 3 PHSTR SH 2 SDO SDO SH 4 4 6 3 2 1 T2 T4 1 KK81...

Страница 27: ...14 A15 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 J13 34PIN_IDC 1 2 3 4 5 6 7 8 9 10 11 12 13 14...

Страница 28: ...1 200 1 2 3 4 5 J3 SMA C19 01uF CLK1 CLK1 CLK1C CLK1 CLK1C R14 200 1 2 3 4 5 J4 SMA C20 01uF CLK2 CLK2 CLK2C CLK2 CLK2C DAC5686 B 3 5 J SETON Y DEWONCK 1 PART NOT INSTALLED NOTES 3 1 4 6 2 T4 TCM4 1W...

Страница 29: ...5 12 J1 DB25F RA R34 10K R35 10K R36 10K R37 10K R3 10 SDENB SCLK SDIO C21 1uF 3 3V_SER SDIO SCLK SDENB SH 1 SH 1 SH 1 OE1_ 1 1A1 2 1A2 4 1A3 6 1A4 8 2A1 11 2A2 13 2A3 15 2A4 17 GND 10 2Y4 3 2Y3 5 2Y2...

Страница 30: ...VDD FB2 C28 10uF C42 1uF C48 0 01uF C54 47 uF C30 10uF C43 1uF C49 0 01uF FB3 1 8VD VD J8 RED VD C55 47 uF 3 3VPLL FB5 C32 10uF C45 1uF C51 0 01uF C57 47 uF 3 3VCLK FB6 C35 10uF C46 1uF C52 0 01uF C58...

Страница 31: ...temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engineer or visit www ti com esh No license is granted under any pa...

Страница 32: ...iness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product wou...

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