Board Layout, Schematic, and Bill of Materials
12
SLUUBR4A – February 2018 – Revised December 2018
Copyright © 2018, Texas Instruments Incorporated
bq25970 PWR893 Evaluation Module
Figure 12. bq25970EVM-893 Bottom Layer Assembly
3.1.1
PCB Layout Guideline
The bq25970 supports up to a 8-A charge current. It is critical to maximize the BUS and VOUT Cu
trace. TI recommends following the PCB layout guidelines:
1. VBUS traces should be as short and wide as possible to accommodate for high current.
2. Minimize losses through connectors wherever possible, as the losses in these connectors will
contribute a significant amount to the total power loss.
3. Use vias under the exposed thermal pad for thermal relief.
4. Place low ESR bypass capacitors to ground for VBUS, PMID, and VOUT. The capacitor should be
placed as close to the device pins as possible.
5. The CFLY pads should be as small as possible, and the CFLY caps placed as close as possible to the
device, as these are switching pins and this will help reduce EMI.
6. Connect all quiet signals to the AGND pin(s).
7. Connect all power signals to the GND pin(s).
8. Do not route so the power planes are interrupted by signal traces.
