PCB Layout Guideline
5
PCB Layout Guideline
As for all switching power supplies, the PCB layout is an important step in the design, especially at high
peak currents and high switching frequencies. If the layout is not carefully done, the boost
converter/charger and buck converter could show stability problems as well as EMI problems. Therefore,
use wide and short traces for the main current path and for the power ground paths. The input and output
capacitors as well as the inductors should be placed as close as possible to the IC. For the boost charger,
the first priority are the output capacitors, including the 0.1-µF bypass capacitor (CBYP), followed by
CSTOR, which should be placed as close as possible between VSTOR, pin 19, and VSS, pin 1. Next, the
input capacitor, CIN, should be placed as close as possible between VIN_DC, pin 2, and VSS, pin 1. Last
in priority is the boost converter inductor, L1, which should be placed close to LBOOST, pin 20, and
VIN_DC, pin 2. It is best to use vias and bottom traces for connecting the inductors to their respective pins
instead of the capacitors.
To minimize noise pickup by the high impedance voltage setting nodes (VBAT_OV, OK_PROG, and
OK_HYST), the external resistors should be placed so that the traces connecting the midpoints of each
divider to their respective pins are as short as possible. When laying out the non-power ground return
paths (for example from resistors and CREF), it is recommended to use short traces as well, separated
from the power ground traces and connected to VSS pin 15. This avoids ground shift problems, which can
occur due to superimposition of power ground current and control ground current. The PowerPAD™
should not be used as a power ground return path.
The remaining pins are either NC pins, that should be connected to the PowerPad as shown below, or
digital signals with minimal layout restrictions.
In order to maximize efficiency at light load, the use of voltage level setting resistors > 1 M
Ω
is
recommended. However, during board assembly, contaminants such as solder flux and even some board
cleaning agents can leave residue that may form parasitic resistors across the physical resistors or from
one end of a resistor to ground, especially in humid, fast airflow environments. This can result in the
voltage regulation and threshold levels changing significantly from those expected per the installed resistor
values. Therefore, it is recommended that no ground planes be poured near the voltage setting resistors.
In addition, the boards must be carefully cleaned, possibly rotated at least once during cleaning, and then
rinsed with de-ionized water until the ionic contamination of that water is well above 50
Ω
. If this is not
feasible, then it is recommended that the sum of the voltage setting resistors be reduced to at least 5X
below the measured ionic contamination.
19
SLUUAA8 – September 2013
User's Guide for bq25505 Battery Charger Evaluation Module for Energy
Harvesting
Copyright © 2013, Texas Instruments Incorporated
