9.3.6 Input Voltage Based Dynamic Power Management (V
IN(DPM)
)
During the normal charging process, if the input power source is not able to support the programmed or default
charging current and System load, the supply voltage decreases. Once the supply approaches V
IN(DPM)
, the
input DPM current and voltage loops will reduce the input current through the blocking FETs, to prevent the
further drop of the supply. The V
IN(DPM)
threshold is programmable through the I
2
C register from 4.2 V to 4.9 V
in 100-mV steps. It can be disabled completely as well. When the device enters this mode, the charge current
may be lower than the set value and the VINDPM_STAT bit is set. If the 2X timer is set, the safety timer is
extended while V
IN(DPM)
is active. Additionally, termination is disabled. Note that in a condition where the battery
is connected while V
UVLO
<V
IN
< V
IN(DPM)
, the VINDPM loop will prevent the battery from being charged and
PMID will be powered from BAT.
9.3.7 Input Overvoltage Protection and Undervoltage Status Indication
The input overvoltage protection protects the device and downstream components connected to PMID, SYS,
and BAT against damage from overvoltage on the input supply. When V
IN
> V
OVP
an OVP fault is determined to
exist. During the OVP fault, the device turns the battery discharge FET on, sends a single 128-µs pulse on INT,
and the FAULT bits are updated over I
2
C. Once the OVP fault is removed, after the deglitch time, t
DGL_OVP
, STAT
and FAULT bits are cleared and the device returns to normal operation. The FAULT bits are not cleared until they
are read in from I
2
C after the OVP condition no longer exists. The OVP threshold for the device is set to operate
from standard USB sources.
The input under-voltage status indication is used to notify the host or other device when the input voltage falls
below a desired threshold. When V
IN
< V
UVLO
, after the deglitch time t
DGL_UVLO
, a UVLO fault is determined to
exist. During the V
IN
UVLO fault, the device sends a single 128-µs pulse on INT, and the STAT and FAULT bits
are updated over I
2
C. The FAULT bits are not cleared until they are read in from I
2
C after the UVLO condition no
longer exists.
9.3.8 Battery Charging Process and Charge Profile
When a valid input source is connected (V
IN
> V
UVLO
and V
(BAT)
+ V
SLP
< V
IN
< V
OVP
and V
IN
> V
IN(DPM)
), the CE
bit in the control register determines whether a charge cycle is initiated. When the CE bit is 1 and a valid input
source is connected, the battery discharge FET is turned off, and the output at SYS is regulated depending on
the output configuration. A charge cycle is initiated when the CE bit is written to a 0. Alternatively, the CD input
can be used to enable and disable charge.
The device supports multiple battery chemistries for single-cell applications. Charging is done through the
internal battery MOSFET. There are several loops that influence the charge current: constant current loop (CC),
constant voltage loop (CV), input current limit, V
DPPM
, and V
IN(DPM)
. During the charging process, all loops are
enabled and the one that is dominant takes control.
The charge current is regulated to I
CHARGE
until the voltage between BAT and GND reaches the regulation
voltage. The voltage between BAT and GND is regulated to V
BATREG
(CV Mode) while the charge current
naturally tapers down. When termination is enabled, the device monitors the charging current during the CV
mode, and once the charge current tapers down to the termination threshold, I
TERM
, and the battery voltage is
above the recharge threshold, the device terminates charge, and turns off the battery charging FET. Termination
is disabled when any loop is active other than CV.
9.3.9 Dynamic Power Path Management Mode
With a valid input source connected, the power-path management circuitry monitors the input voltage and
current continuously. The current into IN is shared at PMID between charging the battery and powering the
system load at PMID, SYS, and LS/LDO. If the sum of the charging and load currents exceeds the current
that the VIN can support, the input DPM loop(VINDPM) reduces the current going into PMID through the input
blocking FETs. This will cause a drop on the PMID voltage if the system demands more current. If PMID drops
below the DPPM voltage threshold(V
DPPM
), the charging current is reduced by the DPPM loop through the
BATFET in order to stabilize PMID. If PMID continues to drop after BATFET charging current is reduced to zero,
the part enters supplement mode when PMID falls below the supplement mode threshold. Battery termination
is disabled while in DPPM mode. In order to charge the battery, the voltage at PMID has to be greater than
V
BATREG
+ V
DPPM
threshold.
SLUSCZ6A – JANUARY 2018 – REVISED MAY 2021
20
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