The end user can enable the device (exit Ship Mode) by connecting an adapter to IN (V
IN
> V
BAT
+ V
SLP
) or
by toggling the MR button. Note that in the case where an adapter is connected while the MR is still held low
and immediately after the RESET timer has expired ( MR low for t
RESET
), the device will not enter Ship Mode,
but may enter it upon adapter removal (Same behavior as setting the EN_SHIPMODE bit when the adapter is
present). This will not be the case if MR has gone high when the adapter is connected or MR continues to be
held low for a period longer than t
WAKE1
after the adapter is connected.
To exit Ship Mode through and MR press the battery voltage must be above the maximum programmable
BUVLO threshold when V
IN
is not present. Once MR goes low, the device will start to exit Ship Mode, powering
PMID. The device will not complete the transition from Ship Mode until MR has been held low for at least t
WAKE1
.
Only after the transition is complete may the host start I
2
C communication if the device has not entered High
Impedance Mode.
9.3.2 High Impedance Mode
High Impedance mode is the lowest quiescent current state while operating from the battery. During Hi-Z mode
the SYS output is powered by BAT, the MR input is active, and the LSCTRL input is active. All other circuits are
in a low power or sleep state.The LS/LDO output can be enabled in Hi-Z mode with the LSCTRL input. If the
LS/LDO output has been enabled through I
2
C prior to entering Hi-Z mode, it will stay enabled. The CD pin is
used to put the device in a high-impedance mode when battery is present and V
IN
< V
UVLO
. Drive CD high to
enable the device and enter active battery operation when V
IN
is not valid. When the HZ_MODE bit is written by
the host, the I
2
C interface is disabled if only battery is present. To resume I
2
C, the CD pin must be toggled. If the
supply for the CD pull up glitches or experiences a brownout condition , it is recommended to toggle the CD pin
to resume I
2
C communication. The functionality of the pin is shown in
Table 9-1. CD, State Table
CD, STATE
V
IN
< V
UVLO
V
IN
> V
UVLO
L
Hi-Z
Charge Enabled
H
Active Battery
Charge Disabled
9.3.3 Active Battery Only Connected
When the battery above V
BATUVLO
is connected with no input source, the battery discharge FET is turned on.
After the battery rises above V
BATUVLO
and the deglitch time is reached, the SYS output starts to rise. The
current from PMID and SYS is not regulated, but is protected by a short circuit current limit. If the short circuit
limit is reached for the deglitch time (t
DGL_SC
), the battery discharge FET is turned off for the recovery time
(t
REC_SC
). After the recovery time, the battery FET is turned on to test if the short has been removed. If it has not,
the FET turns off and the process repeats until the short is removed. This process protects the internal FET from
over current. During this event PMID will likely droop and cause SYS to go out of regulation.
To provide designers the most flexibility in optimizing their system, an adjustable BATUVLO is provided. When
the voltage drops below the V
BATUVLO
threshold, the battery discharge FET is turned off. Deeper discharge of
the battery enables longer times between charging, but may shorten the battery life. The BATUVLO is adjustable
with a fixed 150-mV hysteresis.
If a valid V
IN
is connected during active battery mode, V
IN
> V
UVLO
, the supplement and battery discharge FET is
turned on when the battery voltage is above the minimum V
BATUVLO
.
Drive CD high or write the CE register to disable charge when V
IN
> V
UVLO
is present. CD is internally pulled
down. When exiting this mode, charging resumes if V
IN
is present, CD is low and charging is enabled.
All HOST interfaces ( CD, SDA/SCL, INT, RESET and LSCTRL) are active no later than 5 ms after SYS reaches
the programmed level.
9.3.4 Voltage Based Battery Monitor
The device implements a simple voltage battery monitor which can be used to determine the depth of discharge.
Prior to entering High-Z mode, the device will initiate a VBMON reading. The host can read the latched value
for the no-load battery voltage, or initiate a reading using VBMON_READ to see the battery voltage under a
known load. The register will be updated and can be read 2 ms after a read is initiated. The VBMON voltage
SLUSCZ6A – JANUARY 2018 – REVISED MAY 2021
18
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