9.6.9 Push-Button Control Register
Memory location 0x08h, Reset State: 0101 01xx
Figure 9-19. Push-Button Control Register
7 (MSB)
6
5
4
3
2
1
0 (LSB)
0
1
0
1
0
1
x
x
R/W
R/W
R/W
R/W
R/W
R/W
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-21. Push-Button Control Register
Bit
Field
Type
Reset
Description
B7 (MSB) MRWAKE1
R/W
0
MR Timer adjustment for WAKE1:
0 – 80 ms < MR
1 – 600 ms < MR
B6
MRWAKE2
R/W
1
MR Timer adjustment for WAKE2:
0 – 1000 ms < MR
1 – 1500 ms < MR
B5
MRREC
R/W
0
0 – After Reset, device enters Ship mode
1 – After Reset, device enters Hi-Z Mode
B4
MRRESET_1
R/W
1
MR Timer adjustment for reset:
00 – 5 s ± 20%
01 – 9 s ± 20%
10 – 11 s ± 20%
11 – 15 s ± 20%
B3
MRRESET_0
R/W
0
B2
PGB_MR
R/W
1
0 – Output functions as PG
1 – Output functions as voltage shifted push-button ( MR) input
B1
WAKE1
R
x
1 – WAKE1 status. Indicates when the device meets the WAKE1
conditions, and is cleared after I
2
C read.
B0 (LSB) WAKE2
R
x
1 – WAKE2 status. Indicates when the device meets the WAKE2
conditions, and is cleared after I
2
C read.
SLUSCZ6A – JANUARY 2018 – REVISED MAY 2021
Copyright © 2021 Texas Instruments Incorporated
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