Pin Descriptions
2-2
2.1
Pin Descriptions
BAT+
cell positive
BAT–
cell negative
PACK+
pack positive
PACK–
pack negative
SDQ
serial communications port
PDET
pack removal detection
STAT
status output
2.2
Schematic
Figure 2–1 is the schematic diagram for the bq2023EVM–001 circuit module
(SLUP142–001).
Figure 2–1. Schematic
J1
1
2
PACK+
BAT+
R2
100 k
Ω
U1
BQ2023PW
R10
100
Ω
RBI
STAT
VCC
SRP
VSS
SRN
SDQ
PDET
8
1
7
2
6
3
5
4
R7
100 k
Ω
PACK–
BAT–
J3
1
2
J4
2
1
SDQ
D3
5.6 V
R8
0.02
Ω
C3
0.1
µ
F
R9
100 k
Ω
C2
0.1
µ
F
R11
100
Ω
C4
0.1
µ
F
C1
0.1
µ
F
R1
1 M
Ω
STAT
PDET
R4
100
Ω
R3
100
Ω
R6
100
Ω
R5
100
Ω
D1
5.6 V
D2
5.6 V
J2
1
2
Optional Components
Содержание bq2023EVM-001
Страница 1: ... May 2002 High Performance Analog Products User s Guide SLUU112 ...
Страница 6: ...vi ...
Страница 14: ...Board Layout 2 4 Figure 2 2 Board Layout continued Layer 2 Mask 1 Mask 2 ...
Страница 16: ...2 6 ...
Страница 20: ...3 4 ...