Interface Details
15
SPRUIE6 – April 2017
Copyright © 2017, Texas Instruments Incorporated
AMIC110 Industrial Communications Engine (AMIC110 ICE)
2.7.2
DDR Timing Control and Software Leveling
See
AM335x DDR PHY register configuration for DDR3 using Software Leveling
for more information
about software leveling.
lists the seed values used as inputs to the Code Composer Studio™ (CCS) based application.
Table 4. Seed Values
Parameters
DDR3 clock frequency
400
MHz
Invert Clkout
0
Trace length (inches)
Byte 0
Byte 1
CK trace
0.94463
0.94463
DQS trace
0.915736
0.797452
Seed values (per byte lane)
WR DQS
0
2
RD DQS
34
34
RD DQS GATE
67
62
Seed values to input to program
WR DQS
0
RD DQS
1A
RD DQS GATE
32
The following code snippet shows the optimum values obtained after running the
DDR3_slave_ratio_search_auto.out file in CCS.
******************************************************
The Slave Ratio Search Program Values are...
***************************************************************
PARAMETER
MAX
|
MIN
| OPTIMUM |
RANGE
***************************************************************
0x06d | 0x007 |
0x03a
| 0x066
DATA_PHY_FIFO_WE_SLAVE_RATIO
0x12c | 0x000 |
0x096
| 0x12c
DATA_PHY_WR_DQS_SLAVE_RATIO
0x070 | 0x003 |
0x039
| 0x06d
DATA_PHY_WR_DATA_SLAVE_RATIO
0x0a8 | 0x03b |
0x071
| 0x06d
**************************************************************