AMIC110 (SoC)
DP83822 (PHY)
PHY_COL
Mode 4
50 K
3.3 V
9 K
PHY1_RXD0
Mode 1
9 K
PHY1_RXD1
Mode 1
9 K
PHY1_RXD2
Mode 1
9 K
PHY1_RXD3
Mode 1
PHY1_LED0
Mode 4
50 K
3.3 V
PHY1_CRS
Mode 4
50 K
3.3 V
PHY1_RXER
Mode 4
50 K
3.3 V
9 K
PHY1_RXDV
Mode 1
2.49 K
R188
4.7 K
3.3 V
R53
PU/PD
disabled
Copyright © 2017, Texas Instruments Incorporated
Interface Details
10
SPRUIE6 – April 2017
Copyright © 2017, Texas Instruments Incorporated
AMIC110 Industrial Communications Engine (AMIC110 ICE)
shows the industrial Ethernet PHY1 strapping resistors.
Figure 8. Industrial Ethernet PHY1 Strapping Resistors
lists the configurations for PHY1. See the hardware bootstrap configurations section of
Robust, Low Power 10/100 Mbps Ethernet Physical Layer Transceiver
for more information.
Table 2. Ethernet PHY1 Strap Configuration
Strap Setting
Pin Name
Strap Function
Value of Strap
Function
Description
Address
COL
PHY_AD0
1
1
RX_D0
PHY_AD1
0
RX_D1
PHY_AD2
0
RX_D3
PHY_AD3
0
Modes of operation
COL
FX_EN
0
10BASE-Te, half duplex
100BASE-TX, half duplex
RX_D3
AN_EN
1
RX_D0
AN_1
1
LED_0
AN_0
0
EEE operation
RX_D1
EEE_EN
0
Disabled
Fast link drop
RX_D2
FLD_EN
0
Disabled
Auto MDIX
RX_ER
AMDIX_EN
1
Disabled
MAC interface
RX_ER
RGMII_EN
0
MII, 24-MHz reference clock
RX_DV
RMII_EN
0
RX_DV
XI_50
0
LED_0
CRS
LED_CFG
1
ON for good link, OFF for no link
LED_1
CRS
LED_SPEED
0
Tri-state condition