Revision History
58
SLOU430A – December 2015 – Revised February 2016
Copyright © 2015–2016, Texas Instruments Incorporated
Revision History
missing GTX Clk or SysRef clock to the FPGA could be the reason.
❏
Verify that the EVMs are mechanically mated correctly
❏
Verify power supply to both EVMs
❏
Verify jumper settings on the AFE EVM. Particularly inspect J29, J33, J37, J31, J34, and J36.
❏
Use an oscilloscope to test the frequency of the clock at header J36 or J34. This should be a
50-MHz square wave. TP44 should be 200 MHz. If using JESD, also check TP42 near the
LMK04826, this should be either 200 MHz or 400 MHz, by default. Also check TP43.
Figure 69. Read DDR Error for No Capture
Revision History
Changes from Original (October 2015) to A Revision
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Page
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Modified the abstract.
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•
Changed board image and text and renamed the
EVM Hardware Overview
section.
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•
Moved and changed text in the
GUI Software Installation
section.
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•
Moved and changed the section name of the
Quick Views of Evaluation Setups for LVDS Interface
section.
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•
Changed text in the
Quick Views of Evaluation Setups for LVDS Interface
section.
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•
Changed text and section name in the
Testing the EVM Data Capture with LVDS
section.
....................................
•
Completely overhauled the
Software Installation
section.
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•
Added the
Hardware Configuration
section.
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•
Added the
Triggering Options
section.
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•
Added the
Common Hardware Modifications
section.
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•
Added the
AFE5818 EVM Hardware Overview
and
Schematics
sections to Appendix E.
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•
Updated the
Bill of Materials
in Appendix E.
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•
Added the
FAQ and Troubleshooting
section.
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NOTE: Page numbers for previous revisions may differ from page numbers in the current version.