±
90
±
75
±
60
±
45
±
30
±
15
0
100
1000
10000
P
h
a
s
e
(
D
e
g
re
e
)
Input Frequency (Hz)
C048
-----
± 2.5 VREF
-----
± 1.25 VREF
----- ± 0.625 VREF
------ +2.5 VREF
------+1.25VREF
±
6
±
5
±
4
±
3
±
2
±
1
0
100
1000
10000
M
a
g
n
itu
d
e
(
d
B
)
Input Frequency (Hz)
C047
-----
± 2.5*V
REF
-----
± 1.25*V
REF
----- ± 0.625*V
REF
------ +2.5*V
REF
------+1.25*V
REF
SBAS582C – JULY 2014 – REVISED APRIL 2015
8.3.4 Programmable Gain Amplifier (PGA)
The devices offer a programmable gain amplifier (PGA) at each individual analog input channel, which converts
the original single-ended input signal into a fully-differential signal to drive the internal 16-bit ADC. The PGA also
adjusts the common-mode level of the input signal before being fed into the ADC to ensure maximum usage of
the ADC input dynamic range. Depending on the range of the input signal, the PGA gain can be accordingly
adjusted by setting the Range_CH
n
[3:0]
(n = 0 to 3 or 7)
bits in the program register. The default or power-on
state for the Range_CH
n
[3:0] bits is 000, which corresponds to an input signal range of ±2.5 × V
REF
.
lists
the various configurations of the Range_CH
n
[3:0] bits for the different analog input voltage ranges.
The PGA uses a very highly-matched network of resistors for multiple gain configurations. Matching between
these resistors and the amplifiers across all channels is accurately trimmed to keep the overall gain error low
across all channels and input ranges.
Table 3. Input Range Selection Bits Configuration
Range_CHn[3:0]
ANALOG INPUT RANGE
BIT 3
BIT 2
BIT 1
BIT 0
±2.5 × V
REF
0
0
0
0
±1.25 × V
REF
0
0
0
1
±0.625 × V
REF
0
0
1
0
0 to 2.5 × V
REF
0
1
0
1
0 to 1.25 × V
REF
0
1
1
0
8.3.5 Second-Order, Low-Pass Filter (LPF)
In order to mitigate the noise of the front-end amplifiers and gain resistors of the PGA, each analog input channel
of the ADS8684 and ADS8688 features a second-order, antialiasing LPF at the output of the PGA. The
magnitude and phase response of the analog antialiasing filter are shown in
and
,
respectively. For maximum performance, the –3-dB cutoff frequency for the antialiasing filter is typically set to
15 kHz. The performance of the filter is consistent across all input ranges supported by the ADC.
Figure 55. Second-Order LPF Magnitude Response
Figure 56. Second-Order LPF Phase Response
8.3.6 ADC Driver
In order to meet the performance of a 16-bit, SAR ADC at the maximum sampling rate (500 kSPS), the sample-
and-hold capacitors at the input of the ADC must be successfully charged and discharged during the acquisition
time window. This drive requirement at the inputs of the ADC necessitates the use of a high-bandwidth, low-
noise, and stable amplifier buffer. Such an input driver is integrated in the front-end signal path of each analog
input channel of the device. During transition from one channel of the multiplexer to another channel, the fast
integrated driver ensures that the multiplexer output settles to 16-bit accuracy within the acquisition time of the
ADC, irrespective of the input levels on the respective channels.
Copyright © 2014–2015, Texas Instruments Incorporated
25
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