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Software Control

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SLAU467D – November 2012 – Revised February 2017

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ADS42JB46, ADS42JB49, and ADS42JB69 Evaluation Module

Table 1. Input and Output Connectors and Jumper Descriptions of the ADS42JBxxEVM

Component

Description

J1 (AINP)

Single-ended analog input for channel A

J2 (BINP)

Single-ended analog input for channel B

J19 (EXT_ADC_CLK)

Single-ended ADC clock input

J8 (+5V)

Positive power connection (5 V)

J9 (GND)

Negative power connection (GND)

J13 (Main PWR)

5-V input for provided power cable

J14 (REF OSC_IN)

External reference option for LMK04828, REFOUT1 source on J16 and CPLD_CLK

J16 (REFOUT1)

10-MHz CMOS level reference output or frequency of REF OSC_IN if option selected

J6 (USB)

USB connection

JESD204B FMC interface connector

J5 (LMK SYNC)

LMK04828 sync input

J7 (LMK CLKIN1_P)

CLKIN0 input for LMK04828. Option to provide an external clock source to the LMK in place of on-
board 100-MHz VCXO.

J10 (CLKOUT10P)

DCLKOUT6p from LMK04828. Default is LVPECL at 250 MHz.

J15 (CLKOUT10N)

DCLKOUT6n from LMK04828. Default is LVPECL at 250 MHz.

J17 (CLKOUT12P)

SDCLKOUT7p from LMK04828. Default is LVPECL at 6.25 MHz.

J4 (CLKOUT12M)

SDCLKOUT7p from LMK04828. Default is LVPECL at 6.25 MHz.

J18 (PROG CPLD)

JTAG interface for CPLD U3

SW1 (ADC_RESET)

Switch to reset the ADC using the RESET input pin

SW3 (CPLD)

Switch inputs to CPLD. Currently not used.

SW2 (Reset CPLD)

CPLD reset

SJP12

ADC CNTRL1 pin. Not used by ADC. Connected to GND.

JP3

ADC CNTRL2 pin. Not used by ADC. Connected to GND.

JP6 (XO_PWR)

Provides power to VCXO Y2 or oscillator Y3

SJP3 (REF_SEL)

Selects input or external reference source for LMK, J16 and CPLD. Default is internal 10-MHz source.

JP2 (CDC_CLK)

Reference clock buffer output enable

JP5 (REF_PWR)

Power enable for 10-MHz reference oscillator

SJP1 (REF_EN)

Enable for 10-MHz reference oscillator

SJP4-SJP11

USB/FMC Interface select. Default is using USB.

SJP2 (WP)

EEPROM write protect.

JP4 (ENABLE)

U11 enable. Install jumper to disable switcher U11. Default is uninstalled.

JP1 (PWRGD)

Test point for power good output pin from U11.

Software Control

This section provides installation instructions for the ADS42JBxx GUI and descriptions of the various
controls. Please note, any illustration and textual references to ADS42JB69 or ADS42JBx9 in this section
apply to the ADS42JB46 as well.

2.1

Installation Instructions for ADS42JBxxEVM GUI

1. Download the software installation package (

SLAC544

) from the ADS42JBxxEVM product page.

2. Extract the files from the zip file named

ADS42JBx9 GUI vXpY installer.zip

where

XpY

represents the

version number.

3. Run

setup.exe

and follow the installation prompts to install the software.

4. After successfully installing the software, start the GUI by going to

Start Menu

→

All Programs

→

Texas Instruments ADCs

→

ADS42JBxx GUI

Содержание ADS42JB46

Страница 1: ...828 clock jitter cleaner to provide a low jitter phase noise sampling clock to the ADC This user s guide outlines the steps to quickly evaluate the performance of the ADS42JBxx ADC by capturing and displaying signal waveforms using the TSW14J5xEVM and the High Speed Data Converter Pro GUI software The EVM schematics BOMs and layout files are found in the design package under the ADS42JBxxEVM produ...

Страница 2: ...ered analog input and outputs featuring a JESD204B interface The ADS42JB46 14 bit is a low power 160 MSPS ADC version of the same family of ADC s The EVM has transformer coupled analog inputs accommodating a wide range of signal sources and frequencies The onboard LMK04828 provides an ultra low jitter and phase noise ADC sample clock along with system reference clocks SYSREF for the ADC and the ma...

Страница 3: ...mber 2012 Revised February 2017 Submit Documentation Feedback Copyright 2012 2017 Texas Instruments Incorporated ADS42JB46 ADS42JB49 and ADS42JB69 Evaluation Module 1 2 Block Diagram The block diagram for the ADS42JB69EVM is shown in Figure 1 The various inputs outputs and jumper configurations of the ADS42JBxxEVM are described in Table 1 Figure 1 Block Diagram of the ADS42JBxxEVM ...

Страница 4: ...T Switch to reset the ADC using the RESET input pin SW3 CPLD Switch inputs to CPLD Currently not used SW2 Reset CPLD CPLD reset SJP12 ADC CNTRL1 pin Not used by ADC Connected to GND JP3 ADC CNTRL2 pin Not used by ADC Connected to GND JP6 XO_PWR Provides power to VCXO Y2 or oscillator Y3 SJP3 REF_SEL Selects input or external reference source for LMK J16 and CPLD Default is internal 10 MHz source J...

Страница 5: ...B into both EVMs Plug the other end of USB to the PC or laptop running the ADS42JBxx software and HSDC Pro software Note When plugging the ADS42JBxxEVM board into the computer through the USB cable for the first time you are prompted to install the USB drivers Microsoft Windows XP If Windows XP does not automatically install the drivers follow the prompts on the screen to do so Do not let Windows ...

Страница 6: ...e Figure 3 ADS42JBxx EVM GUI Setup 6 Start the ADS42JBxxEVM software Figure 3 On Windows platforms start the ADS42JBxx EVM GUI software from Start All Programs Texas Instruments ADCs ADS42JBxx 7 Go to Low Level View and click the Load Config button ADS42JB69_EVM_LMF421_250M cfg This configuration file should be located in the GUI software installation directory The configuration file sets the ADC ...

Страница 7: ...ose based on the device and mode being evaluated Table 2 ADC device ini file selection in HSDC Pro Device Mode HSDC Pro ini file ADS42JB46 20x ADS42JB46_LMF_222 ADS42JB46 10x ADS42JB46_LMF_421 ADS42JB49 20x ADS42JB49_LMF_222 ADS42JB49 10x ADS42JB49_LMF_421 ADS42JB69 20x ADS42JB69_LMF_222 ADS42JB69 10x ADS42JB69_LMF_421 10 After selecting the appropriate ADC click Yes when prompted to download firm...

Страница 8: ...aluation Module 14 Connect an analog signal to analog INP or analog INM and capture the data again from the ADC Figure 5 shows data captured from the ADC with a 25 MHz sinusoid at analog INP and sampling rate of 250 MSPS You can switch between data from channel 1 and 2 of the ADC from the HSDC Pro GUI interface Refer to the HSDC Pro GUI users guide SLWU087 for more details Figure 5 ADC Data Captur...

Страница 9: ...LAS621 ADS42JBx9 SLAS900 for more detailed explanations of the register fields 3 1 Top Level GUI Controls Figure 6 shows the top level view of the GUI which contains the block diagram of the ADS42JBxx Along the top of the GUI are four tabs that can be used to navigate and configure the device Also on the top right is the The Reconnect FTDI Button this Button can be used to initialize the FTDI devi...

Страница 10: ...2017 Texas Instruments Incorporated ADS42JB46 ADS42JB49 and ADS42JB69 Evaluation Module 3 2 ADC Controls Clicking the ADS42JBxx tab brings up the ADC controls as seen in Figure 7 The ADS42JBxx tab provides various controls to configure the ADC and the JESD204B standard Table 3 describes the controls seen in this window Figure 7 ADC Controls Window of the ADS42JBxx GUI ...

Страница 11: ...annel B Ch B Gain Set gain for channel B between 2 7dB to 6dB Ch B FS Voltage Automatically sets the equivalent Full Scale Input Voltage when the CH B Gain is set Digital Test Patterns Ch A Test Pattern Select from 12 different test patterns to be applied as inputs to JESD block for channel A Ch B Test Pattern Select from 12 different test patterns to be applied as inputs to JESD block for channel...

Страница 12: ...ver to align to the lane boundary per section 5 3 3 5 of the JESD204B specification Testmode EN Generates a long transport layer test pattern mode according to the 5 1 63 clause of the JESD204B specification Scramble Scramble enable bit in the JESD204B interface Insert Frame Align Inserts a frame alignment character K28 7 for the receiver to align to the frame boundary per section 5 3 3 4 of the J...

Страница 13: ...Configuration Sys and Sync and Output Clock tabs Clicking on each option opens a new panel in the GUI for control of that section 3 3 1 PLL1 Configuration By default the PLL1 Configuration tab is shown when LMK04828 tab is selected To the right of the panel is a block diagram shown in Figure 8 This panel controls the PLL1 settings of the LMK04828 Once these values are properly entered and PLL1 bec...

Страница 14: ...ns a new window with a block diagram of PLL2 as shown in Figure 9 This panel controls the PLL2 settings of the LMK04828 Once these values are properly entered and PLL2 becomes locked LED D4 PLL2 Locked on the ADS42JBxxEVM illuminates A wrong divider value would be a reason for this LED not illuminating Use the LMK clock design tools when determining external PLL loop filter components Go to the LM...

Страница 15: ...le 3 3 3 SYSREF and SYNC Clicking SYSREF and SYNC tab opens a new window as shown in Figure 10 This panel controls the SYSREF and SYNC output global settings of the LMK04828 The settings made in this panel apply to all SYSREF outputs Using the SYNC input causes all active clock outputs to share a rising edge as programmed by fixed digital delay The SYNC event must occur for digital delay values to...

Страница 16: ...indow as shown in Figure 11 This panel controls the output clock settings of the LMK04828 The LMK0482x family features a total of 14 PLL2 clock outputs driven from the internal or external VCO The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks Not limited to JESD204B applications each of the 14 outputs can be in...

Страница 17: ...42JB69 Evaluation Module 3 4 Low Level View The Low Level View tab can be used to access the various registers of the LMK04828 and ADS42JBxx High level control of most of these registers is accessible in the ADS42JBxx tab and LMK04828 tab This page also provides the option of saving a register configuration or loading a previously saved configuration Figure 12 shows a screen shot of the Low Level ...

Страница 18: ...Page numbers for previous revisions may differ from page numbers in the current version Changes from C Revision April 2016 to D Revision Page Changed TSW14J56EVM throughout the document to TSW14J5xEVM TSW14J56 to TSW14J5x as well 1 Updated images and text in the Software Control section due to software changes 4 Updated images and text in the Software Operation section due to software changes 9 ...

Страница 19: ...y set forth above or credit User s account for such EVM TI s liability under this warranty shall be limited to EVMs that are returned during the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty If TI elects to repair or replace such EVM TI shall have a reasonable time to repair such EVM or provide replacements Repaired EVMs shall be warr...

Страница 20: ...the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated Antenna types not included in this list having a gain greater than the maximum gain indicated for that type are strictly prohibited for use with this device Concernant les EVMs avec antennes détachables Conformément à la réglementation d Industrie Canada le présent émetteur radio peut fo...

Страница 21: ...ed loads Any loads applied outside of the specified output range may also result in unintended and or inaccurate operation and or possible permanent damage to the EVM and or interface electronics Please consult the EVM user guide prior to connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation even ...

Страница 22: ...COST OF REMOVAL OR REINSTALLATION ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES RETESTING OUTSIDE COMPUTER TIME LABOR COSTS LOSS OF GOODWILL LOSS OF PROFITS LOSS OF SAVINGS LOSS OF USE LOSS OF DATA OR BUSINESS INTERRUPTION NO CLAIM SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN TWELVE 12 MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS OCCURRED 8 2 Specif...

Страница 23: ... TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN including but not limited to any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI product...

Страница 24: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments ADS42JB69EVM ADS42JB46EVM ...

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