Quick Reference
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6
SBAU197A – February 2012 – Revised January 2016
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Copyright © 2012–2016, Texas Instruments Incorporated
ADS1x7xEVM-PDK
3
Quick Reference
Table 3
provides a quick summary of the connections required for operation of the EVM as a standalone
Table 3. Critical Connections
Function
Header/Pin
Pin Name
Description
Interface
SCLK
J4.3
CLKX
SCLK
DIN
J4.11
DX
Data In
DOUT
J4.13
DR
Data Out
Interrupt
J4.15
INT
DRDY/FSYNC
Power
1.8V
J5.7
+1.8VD
Digital supply
3.3V
J5.9
+3.3VD
Digital supply
5.0V
J5.3
+5VA
Analog supply
Analog Inputs
Channels 1-4
J3.1-8
Analog Inputs
Channels 5-8
J1.3-10
Analog Inputs (ADS1178 and
ADS1278 only)
CAUTION
When using the EVM as part of the ADS1278EVM-PDK, the DIP switches S1
and S2 must all be switched so that they are down, toward the center of the
board. Failure to do so may damage the EVM.
3.1
Analog Inputs
The analog inputs for the ADS1278EVM are connected to J1 and J3. Channels 1-4 connect to J3 and
provisions are provided to buffer these signals before being connected to the converter. Switches S4, S5,
S7, and S8 control whether the buffered or unbuffered signal is connected to the ADS1278. Channels 5-8
connect to J1 and have an RC filter available to filter the input before connecting to the converter.
Channels 5-8 do not have provisions for buffering the signal.
3.2
Digital Control
The digital control signals can be applied directly to J4 (top or bottom side).
3.3
Power Supply
The ADS1278EVM requires power rails as follows:
•
5.0V analog supply - supplied by MMB0 motherboard via J13B
•
3.3V digital supply - supplied by MMB0 motherboard
•
1.8V digital supply - supplied by MMB0 motherboard
3.4
Voltage Reference
The ADS1278EVM has two options for the reference voltage. Switch S3 selects the reference voltage
from either the buffered REF5025 or a external reference voltage that is connected to the reference pins
of J3 (J3.18 = REFN and J3.20 = REFP).
