ADS1278EVM Hardware Details
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14
SBAU197A – February 2012 – Revised January 2016
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ADS1x7xEVM-PDK
–
The SCLK input of the converter is driven by the serial port signal CLKX, pin J4.3.
–
The signal from the selected source for the clock (see
Section 5.3
,
Clock Source
) is connected to
the CLKR pin (J4.5) allowing the serial port of a processor to be synchronized to the converters
master clock.
–
The signal from the selected clock source is routed to the CLK input of the converter.
–
Port P10 of the I2C port expander U8 is connected to a logic high level, so that the position of
switch S12 can be read back by software.
•
FS
format configures the signals as follows:
–
The SCLK input of the converter is driven by the serial port signal CLKR, pin J4.5.
–
The signal from the selected clock source is connected to the CLKX pin (J4.3), allowing the serial
port of a processor to be synchronized to the converter's master clock.
–
The CLK input of the converter is driven by the CLKR signal (J4.5). This ensures that the CLK and
SCLK signals have the same phase and the correct ratio as outlined in the data sheet of the
device.
–
Port P10 of the I
2
C port expander U8 is connected to a logic low level, so that the position of S6
can be read back by software.
For use in the ADS1278EVM-PDK, the jumpers on S6 must be installed in the
FS
positions, which is the
factory default setting. See
Figure 1
.
Switching to
SPI
format will allow users to connect the EVM to any SPI-compatible processor not
supporting the frame-sync mode. If this format is selected, keep in mind that the high-speed mode will not
operate at full speed (32.768MHz) because of the limitations outlined in the device product data sheet.
5.5.2
Serial Data Interface, J4
This header/socket provides access to the digital control and serial data pins of the ADC.
All logic levels on J4 are 3.3V CMOS, except for the I
2
C™ pins. These pins conform to 3.3V I
2
C rules.
Table 8
describes the J4 serial interface pins.
(1)
Pin 1 is top left-hand corner, located next to reference designator.
(2)
DOUT1 buffered through a D flip-flop. See
Section 5.5.3.1
below.
Table 8. J4, Serial Interface Header
Signal Name
Pin
Number
(J4)
Signal Name
Function
Synchronize channels input SYNC
1
(1)
2
MODE0
Select bit 0 of converter
MODE
SPI clock SCLK
3
4
DGND
Digital ground
SCLK clock CLKR
5
6
MODE1
Select bit 1 of converter
MODE
DRDY/FSYNC source 1 DRDY/FSYNC
7
8
FORMAT0
Select bit 0 of FORMAT
to select Frame-Sync/SPI
Protocol
DRDY/FSYNC source 2 DRDY/FSYNC
9
10
DGND
Digital ground
ADS1278 SPI data in DIN
11
12
FORMAT1
Select bit 1 of FORMAT
to select Frame-Sync/SPI
Protocol
ADS1278 data out DOUT1
(2)
13
14
FORMAT2
Select bit 2 of FORMAT
to select Frame-Sync/SPI
Protocol
DRDY/FSYNC to DSP
(interrupt)
DRDY/FSYNC
15
16
SCL
I
2
C clock
Can be used to provide a clock
from a processor
CLK
17
18
DGND
Digital ground
Clock source select (SW
mode)
CLK Select
19
20
SDA
I
2
C data
