Texas Instruments ADS1178EVM, Руководство пользователя, Страница: 6 / 52

3.2 Data Output
Digital Interface
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All logic levels on J5 are 3.3V CMOS, except for the I
2
C™ pins. These pins conform to 3.3V I
2
C rules.
Table 3 describes the J5 serial interface pins.
Table 3. J5: Serial Interface Pins
Pin No. Pin Name Signal Name I/O Type Pullup Function
J5.1 CNTL SYNC In High —
J5.2 GPIO0 MODE0 In High —
J5.3 CLKX SCLK In None ADS1278 SPI clock
J5.4 DGND DGND In/Out None Digital ground
J5.5 CLKR CLKR Out None SCLK clock
J5.6 GPIO1 MODE1 In High —
J5.7 FSX DRDY/FSYNC In/Out Low —
J5.8 GPIO2 FORMAT0 In High —
J5.9 FSR DRDY/FSYNC In/Out None —
J5.10 DGND DGND In/Out None Digital ground
J5.11 DX DIN In None ADS1278 SPI data
in
J5.12 GPIO3 FORMAT1 In High —
J5.13 DR DOUT1 Out None ADS1278 data out
J5.14 GPIO4 FORMAT2 In None —
J5.15 /INT DRDY/FSYNC Out None —
J5.16 SCL SCL I
2
C N/A I
2
C clock
J5.17 TOUT CLK In None Can be used to
provide a clock from
a processor
J5.18 DGND DGND In/Out None Digital ground
J5.19 GPIO5 CLK Select — None —
J5.20 SDA SDA I
2
C N/A I
2
C data
Many pins on J5 have weak pull-up/down resistors. These resistors provide default settings for many of
the control pins. Many pins on J5 correspond directly to ADS1278 pins. See the
ADS1278 product data
sheet for complete details on these pins.
Most data communications are directed through DOUT1. The data from all eight channels can be
observed on the DOUT1 pin using the TDM mode. That is the signal that is used by the
ADS1278EVM-PDK to read back and display all the channels. All the data output signals (DOUT1 to
DOUT8) can be monitored on J2.
Figure 1 illustrates the pinout for J2.
6 ADS1178EVM, ADS1278EVM, ADS1178EVM-PDK, and ADS1278EVM-PDK SBAU129C – November 2007 – Revised July 2008
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