Texas Instruments ADC3 J EVM Series, Руководство пользователя

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Introduction
1 Introduction
The family of parts and 32 associated EVMs are categorized in Table 1 .
Table 1. ADC3xxx Family of Parts and EVMs
ADC Device Interface Number of Number Max Msps EVM
channels of bits
ADC3221 sLVDS Dual 12 25 ADC3221EVM
(1)
ADC3222 12 50 ADC3222EVM
(1)
ADC3223 12 80 ADC3223EVM
(1)
ADC3224 12 125 ADC3224EVM
ADC3241 14 25 ADC3241EVM
(1)
ADC3242 14 50 ADC3242EVM
(1)
ADC3243 14 80 ADC3243EVM
(1)
ADC3244 14 125 ADC3244EVM
ADC3421 sLVDS Quad 12 25 ADC3421EVM
(1)
ADC3422 12 50 ADC3422EVM
(1)
ADC3423 12 80 ADC3423EVM
(1)
ADC3424 12 125 ADC3424EVM
ADC3441 14 25 ADC3441EVM
(1)
ADC3442 14 50 ADC3442EVM
(1)
ADC3443 14 80 ADC3443EVM
(1)
ADC3444 14 125 ADC3444EVM
ADC32J22 JESD204B Dual 12 50 ADC32J22EVM
(1)
ADC32J23 12 80 ADC32J23EVM
(1)
ADC32J24 12 125 ADC32J24EVM
(1)
ADC32J25 12 160 ADC32J25EVM
(1)
ADC32J42 14 50 ADC32J42EVM
(1)
ADC32J43 14 80 ADC32J43EVM
(1)
ADC32J44 14 125 ADC32J44EVM
(1)
ADC32J45 14 160 ADC32J45EVM
ADC34J22 JESD204B Quad 12 50 ADC34J22EVM
ADC34J23 12 80 ADC34J23EVM
(1)
ADC34J24 12 125 ADC34J24EVM
(1)
ADC34J25 12 160 ADC34J25EVM
ADC34J42 14 50 ADC34J42EVM
(1)
ADC34J43 14 80 ADC34J43EVM
(1)
ADC34J44 14 125 ADC34J44EVM
ADC34J45 14 160 ADC34J45EVM
(1)
EVM is scheduled for release at a later date.
There are 3 package sizes and pinouts for all of these parts. The sLVDS dual devices use a 7 × 7 mm,
48-pin QFN, the sLVDS quad devices use an 8 × 8 mm, 56-pin QFN, and the dual and quad JESD204B
device share the same package using a 7 × 7 mm 48-pin QFN.
The Dual ADCs comprise 2 buffered inputs, 2 ADC cores, and a common input clock circuit. The quad
ADCs comprise 4 buffered inputs, 4 ADC cores and a common input clock circuit. The sLVDS versions
have a 2-wire interface per ADC (2 pairs of p/n signals) – for the dual this means 2 sets of 2-wire
interfaces (4 p/n pairs), the quad would have 4 sets of 2-wire interfaces (8 p/n pairs). Each of these 2 wire
interfaces can be operated in 1-wire mode (14x serialization) or 2-wire mode (7x serialization). For the 12
bit devices this equates to 12x and 6x serialization. The JESD204B versions have 1 lane per ADC core.
For the dual this means there will be 2 lanes per device and 4 lanes per device for the quad. Please refer
to the data sheet for more information on sLVDS serialization and JESD204B lane configurations.
3 SLAU579A – June 2014 – Revised September 2014 ADC3xxx, ADC3xJxx EVM User’s Guide
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