Software Control
2.2.1
ADC3xxxx Control Options
The ADC3xxxx family shares some common registers. These common registers are organized within the
common tab. Other specific device registers are in specific device tabs for the ADC3xxxx family and the
LMK04828 for the JESD204B devices. For a more detailed description of each register, please see the
data sheet.
Common Register Tab
illustrates the following parts of the common tab.
•
Software Reset – Resets the registers to default configuration – similar to pressing SW1, self clearing
•
Global Power Down – power down the entire chip, default 0
•
ADC Standby – All ADCs enter standby mode, default 0
•
Configure PwDn pin function – either global power down or ADC standby mode
•
Data Format – 0 – 2s Complement, 1- Offset Binary, default 0
•
Disable SYSREF BUF – Disable SYSREF Buffer, default 0
•
Clk Diver – Internal clock divider to allow harmonic clocking, a higher frequency clock can be provided
to the ADC and then divided down to the desired sample rate.
Figure 8. Common Tab
13
SLAU579A – June 2014 – Revised September 2014
ADC3xxx, ADC3xJxx EVM User’s Guide
Copyright © 2014, Texas Instruments Incorporated
