TPMC816 V.2.1 User Manual Issue 2.1.0
Page 16 of 22
5 Configuration Hints
5.1 PCI Interrupt Control/Status Register (Address
0x4C)
Both CAN controllers generate interrupts at pin INTA# of the PCI bus. The interrupt status can be read
at the Interrupt Status Register INTCSR of the PCI Controller PCI9030.
Bit
Description
Access
Reset
Value
31:8 unused
R
0
7 Software
Interrupt
R/W
0
6
PCI Interrupt Enable
R/W
1
5
CAN Controller 1 Interrupt Status
R
0
4
Local Interrupt 2 Polarity
R/W
0
3
Local Interrupt 2 Enable
R/W
1
2
CAN Controller 0 Interrupt Status
R
0
1
Local Interrupt 1 Polarity
R/W
0
0
Local Interrupt 1 Enable
R/W
1
Table 5-1 : Interrupt Control/Status Register INTCSR (Address 0x4C)
To enable or disable the interrupts use only the CAN controller Control Register bit 1 (PCI Base
Address 2 + 0x0000 or PCI Base Address 2 + 0x0100). For more details please refer to the
Innovasic IA82527 data sheet which is part of the TPMC816-ED Engineering Documentation.
5.2 Software Reset (Controller and LRESET#)
A host on the PCI bus can set the software reset bit in the Miscellaneous Control Register (CNTRL;
0x50) of the PCI Controller PCI9030 to reset the Controller and assert LRESET# output. The PCI9030
remains in this reset condition until the PCI host clears the software reset bit.
