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TPMC816 V.2.1 User Manual Issue 2.1.0 

Page 13 of 22 

4.2 Local Configuration Register (LCR) 

After reset, the PCI9030 Local Configuration Registers are loaded from the on board serial 
configuration EEPROM. 

The PCI base address for the PCI9030 Local Configuration Registers is PCI9030 PCI Base 
Address 0 (PCI Memory Space) (Offset 0x10 in the PCI9030 PCI Configuration Register Space) 
or PCI9030 PCI Base Address 1 (PCI I/O Space) (Offset 0x14 in the PCI9030 PCI Configuration 
Register Space). 

 

Do not change hardware dependent bit settings in the PCI9030 Local Configuration Registers. 

 
 

Offset from 

PCI Base 

Address 

Register 

Value 

Description 

0x00 

Local Address Space 0 Range 

0x0FFFFE00 (-10) 
0x0FFFFF00 (-11) 

Memory Space CAN 

0x04 

Local Address Space 1 Range 

0x00000000 

Not used 

0x08 

Local Address Space 2 Range 

0x00000000 

Not used 

0x0C 

Local Address Space 3 Range 

0x00000000 

Not used 

0x10 

Local Exp. ROM Range 

0x00000000 

Not used 

0x14 

Local Re-map Register Space 0 0x00000001 Enabled, Offset 0 

0x18 

Local Re-map Register Space 1 

0x00000000 

Not used 

0x1C 

Local Re-map Register Space 2 

0x00000000 

Not used 

0x20 

Local Re-map Register Space 3 

0x00000000 

Not used 

0x24 

Local Re-map Register ROM 

0x00000000 

Not used 

0x28 

Local Address Space 0 Descriptor 

0x5400C042 

Local Timing 

0x2C 

Local Address Space 1 Descriptor 

0x00000000 

Not used 

0x30 

Local Address Space 2 Descriptor 

0x00000000 

Not used 

0x34 

Local Address Space 3 Descriptor 

0x00000000 

Not used 

0x38 

Local Exp. ROM Descriptor 

0x00000000 

Not used 

0x3C 

Chip Select 0 Base Address 

0x00000081 

Chip select CAN0 

0x40 

Chip Select 1 Base Address 

0x00000181 

Chip select CAN1 

0x44 

Chip Select 2 Base Address 

0x00000000 

Not used 

0x48 

Chip Select 3 Base Address 

0x00000000 

Not used 

0x4C Interrupt 

Control/Status 0x00000049 Interrupt 

configuration 

0x4E 

EEPROM Write Protect Boundary 0x00000000 No 

write protection 

0x50 

Miscellaneous Control Register 

0x00780000 

Retry delay = max 

0x54 

General Purpose I/O Control 

0xA4920224 

All pins are outputs 

0x70 

Hidden1 Power Management data select 

0x00000000 

Not used 

0x74 

Hidden 2 Power Management data scale

0x00000000 

Not used 

Table 4-3 :  PCI9030 Local Configuration Register 

Содержание TPMC816

Страница 1: ...Independent Channels Extended CAN Bus PMC Module Version 2 1 User Manual Issue 2 1 0 October 2011 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 4058 0 Fax 49 0 4101 4058...

Страница 2: ...bH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the devic...

Страница 3: ...efault values for Hot Swap Register June 2002 1 2 General Revision December 2002 1 3 Corrections in PCI Target Chip Register Description Updated Block Diagram for P14 I O Added I O Connection Note Jan...

Страница 4: ...r 11 4 1 2 PCI Base Address Initialization 12 4 2 Local Configuration Register LCR 13 4 3 Configuration EEPROM 14 4 4 Local Software Reset 15 5 CONFIGURATION HINTS 16 5 1 PCI Interrupt Control Status...

Страница 5: ...Controller Channel 1 CANCH1 10 Table 4 1 PCI9030 Header 11 Table 4 2 PCI9030 PCI Base Address Usage 12 Table 4 3 PCI9030 Local Configuration Register 13 Table 4 4 Configuration EEPROM TPMC816 10 14 Ta...

Страница 6: ...lacement for the Intel 82527 CAN controller Both channels are completely independent and support CAN specification 2 0 part A and B Standard 11 bit identifier and extended 29 bit identifier Each chann...

Страница 7: ...ohms selectable by jumper for each channel Transfer Rate Up to 1 Mbps at bus line length of up to 40 m Isolation CAN bus isolated by optocouplers I O Interface Front panel TPMC816 10 two DB9 male con...

Страница 8: ...3 Memory Address Map Address Symbol Description CAN Controller Channel 0 CANCH0 0x0000 Control Register 0x0001 Status Register 0x0002 CPU Interface Register 0x0003 Reserved 0x0004 0x0005 High Speed R...

Страница 9: ...CANCH0 Address Symbol Description CAN Controller Channel 1 CANCH1 0x0100 Control Register 0x0101 Status Register 0x0102 CPU Interface Register 0x0103 Reserved 0x0104 0x0105 High Speed Read Register 0x...

Страница 10: ...0x0190 0x019E Message 9 0x019F P1CONF 0x01A0 0x01AE Message A 0x01AF P2CONF 0x01B0 0x01BE Message B 0x01BF P1IN 0x01C0 0x01CE Message C 0x01CF P2IN 0x01D0 0x01DE Message D 0x01DF P1OUT 0x01E0 0x01EE M...

Страница 11: ...2 for Local Address Space 0 Y FFFFFE00 10 FFFFFF00 11 0x1C PCI Base Address 3 for Local Address Space 1 Y 00000000 0x20 PCI Base Address 4 for Local Address Space 2 Y 00000000 0x24 PCI Base Address 5...

Страница 12: ...OM mapping starting at bit location 11 the first bit set to 1 determines the required PCI Expansion ROM size For example if bit 5 of a PCI Base Address Register is detected as the first bit set to 1 t...

Страница 13: ...fset 0 0x18 Local Re map Register Space 1 0x00000000 Not used 0x1C Local Re map Register Space 2 0x00000000 Not used 0x20 Local Re map Register Space 3 0x00000000 Not used 0x24 Local Re map Register R...

Страница 14: ...xFE00 0x0000 0x0000 0x30 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0001 0x40 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x50 0x5400 0xC042 0x0000 0x0000 0x0000 0x0000 0x0000 0x00...

Страница 15: ...FF 0xFFFF 0xFFFF 0xFFFF 0xB0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xC0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xD0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF...

Страница 16: ...Interrupt Status R 0 1 Local Interrupt 1 Polarity R W 0 0 Local Interrupt 1 Enable R W 1 Table 5 1 Interrupt Control Status Register INTCSR Address 0x4C To enable or disable the interrupts use only th...

Страница 17: ...perate in Big or Little Endian Mode Big Endian Little Endian 32 Bit 32 Bit Byte 0 D 31 24 Byte 0 D 7 0 Byte 1 D 23 16 Byte 1 D 15 8 Byte 2 D 15 8 Byte 2 D 23 16 Byte 3 D 7 0 Byte 3 D 31 24 16 Bit uppe...

Страница 18: ...e of 0 indicates Little Endian For further information please refer to the PCI9030 manual which is also part of the TPMC816 Engineering Documentation Use the PCI Base Address 0 Offset or PCI Base Addr...

Страница 19: ...J5 1 2 installed Bus line termination for CAN bus channel 1 active Jumper J8 J9 1 2 installed To set the termination of a CAN bus I O channel always use both jumpers for that channel 6 2 Physical Int...

Страница 20: ...s Figure 6 2 Typical operating circuit I O Connection Note Please note that on the TPMC816 1x the P14 back I O connector is always populated and is connected in parallel to the front I O connector Do...

Страница 21: ...speed or mod RS485 3 Ground channel 0 4 NC 5 NC 6 Ground channel 0 7 High level CAN voltage input output Selectable CAN high speed or mod RS485 8 NC 9 NC Table 7 1 DB9 Male Connector Channel 0 Pin No...

Страница 22: ...peed or mod RS485 13 High level CAN voltage input output channel 1 Selectable CAN high speed or mod RS485 14 Ground channel 1 15 NC 16 32 NC Table 7 3 Mezzanine Card Connector P14 Please note that on...

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