TPMC371 User Manual Issue 1.1.5
Page 9 of 22
3 Local Space Addressing
3.1 XR17D158 Local Space Configuration
The local on board addressable regions are accessed from the PCI side by using the XR17D158 local
space.
XR17D158 PCI Base
Address
(Offset in PCI
Configuration
Space)
PCI
Space
Mapping
Size
(Byte)
Port
Width
(Bit)
Endian
Mode
Description
0 (0x10)
MEM
4096
32
BIG
Device Configuration
Space
Table 3-1 : XR17D158 Local Space Configuration
3.2 Device Configuration Space
PCI Base Address:
XR17D158 PCI Base Address 0 (Offset 0x10 in PCI Configuration
Space).
The TPMC371 uses the Exar XR17D158 Octal UART to provide and control the 8 channels.
Device Configuration Space
Content
PCI Address
Size
(Bit)
UART 0 Register Set
PCI Base Address 0 + (0x0000 to 0x007F)
32
Device Configuration Registers
PCI Base Address 0 + (0x0080 to 0x009F)
32
UART 0 Register Set
PCI Base Address 0 + (0x0100 to 0x01FF)
32
UART 1 Register Set
PCI Base Address 0 + (0x0200 to 0x03FF)
32
UART 2 Register Set
PCI Base Address 0 + (0x0400 to 0x05FF)
32
UART 3 Register Set
PCI Base Address 0 + (0x0600 to 0x07FF)
32
UART 4 Register Set
PCI Base Address 0 + (0x0800 to 0x09FF)
32
UART 5 Register Set
PCI Base Address 0 + (0x0A00 to 0x0BFF)
32
UART 6 Register Set
PCI Base Address 0 + (0x0C00 to 0x0DFF)
32
UART 7 Register Set
PCI Base Address 0 + (0x0E00 to 0x0FFF)
32
Table 3-2 : Device Configuration Space
All registers can be accessed in 8, 16 or 32 bit width with exception to one special case: When reading
the receive data together with its LSR register content, the host must read them in 16 or 32 bits format
in order to maintain integrity of the data byte with its associated error flags.
