Tews Technologies TPMC371-10, Руководство пользователя

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TPMC371 User Manual Issue 1.1.5 Page 12 of 22
3.2.3 UART Channel Configuration Registers
Each UART channel has its own set of internal UART configuration registers for its own operation
control and status reporting. The following table provides the register offsets within a register set,
access types and access control:
Register
Offset Comment Register Access Reset
Value
16550 Compatible
R LCR[7] = 0 RHR – Receive Holding Register
THR – Transmit Holding Register
W
0xXX 0x00
LCR[7] = 1 DLL – Baud Rate Generator Divisor Latch Low R/W 0xXX
LCR[7] = 0 IER – Interrupt Enable Register R/W 0x00 0x01
LCR[7] = 1 DLM – Baud Rate Generator Divisor Latch High R/W 0xXX
R 0x01 0x02 ISR – Interrupt Status Register
FCR – FIFO Control Register
W 0x00
0x03 LCR – Line Control Register R/W 0x00
0x04 MCR – Modem Control Register R/W 0x00
R 0x05 LSR – Line Status Register
Reserved
W
0x60
R 0x06 MSR – Modem Status Register
MSR – Auto RS485 Delay (not supported by the
TPMC371)
W
0xX0
0x07 User Data SPR – Scratch Pad Register R/W 0xFF
Enhanced Registers
0x08 FCTR – Feature Control Register R/W 0x00
0x09 EFR – Enhanced Function Register R/W 0x00
R 0x0A TXCNT – Transmit FIFO Level Counter
TXTRG – Transmit FIFO Trigger Level
W
0x00
R 0x0B RXCNT – Receiver FIFO Level Counter
RXTRG – Receiver FIFO Trigger Level
W
0x00
R 0x0C Xchar – Xon, Xoff Received Flags
Xoff-1 – Xoff Character 1
W
0x00
R 0x0D Reserved
Xoff-2 – Xoff Character 2
W
0x00
R 0x0E Reserved
Xon-1 – Xon Character 1
W
0x00
R 0x0F Reserved
Xon-2 – Xon Character 2
W
0x00
Table 3-6 : UART Channel Configuration Registers