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GMODE.CMOD = '0' (Hold Mode):

After completing a descriptor the DMAC checks the HOLD bit (previously read with the transmit descriptor). If
HOLD = 0, it branches to the next transmit descriptor. Otherwise the corresponding DMAC transmit channel
is deactivated as long as the host CPU does not request reactivation via the GCMDR register (either transmit
poll request or action request with ’IDT’ command).

GMODE.CMOD = '1' (Last Address Mode):

After completing a descriptor the DMAC checks if the first (current) transmit descriptor address (FTDA) is
equal to the last transmit descriptor address (LTDA) stored in the corresponding channel specific on-chip
registers. When both addresses differ, it branches to the next transmit descriptor. Otherwise the
corresponding DMAC transmit channel is deactivated as long as the host CPU does not write a new address
to the LTDA register or provides an action request with the ’IDT’ command.

HOLD: Hold Bit

Only valid if GMODE.CMODE = '0' (Hold Mode).

Used for descriptor list end control.

HOLD = '0':

A next descriptor is available in the shared memory. After checking the HOLD bit the DMAC branches to the
next transmit descriptor.

HOLD = '1':

The current descriptor is the last one (currently) available for the DMAC. The corresponding DMAC channel
is deactivated for transmit direction as long as the microprocessor does not request an activation via the
CMDR register.

NO: Byte Number

NO defines the number of bytes (stored in the data section) to be transmitted. Thus the maximum length of
the data buffer is 8191 bytes (NO = 0x1FFF). A transmit descriptor and the corresponding data section must
contain at least either one data byte or a frame end indication. Otherwise a DMA controller interrupt with
’ERR’ bit set is generated.

HI: Host Initiated Interrupt

If the HI bit is set, the corresponding DMAC generates an HI interrupt after transferring all data bytes of the
current transmit data section.

Next Transmit Descriptor Pointer:

This 32-bit pointer contains the start address of the next transmit descriptor. After fetching the indicated
number of data bytes, the DMAC branches to the next transmit descriptor. The transmit descriptor is read
entirely at the beginning of the transmit descriptor processing and is stored in on-chip memory. Therefore
when the DMAC branches to a (next) descriptor all descriptor information must be valid. This pointer is not
used if a transmitter reset or initialization channel command is detected while the DMAC still reads data from
the current transmit descriptor. In this case the value in the BTDA register is used as a pointer for the next
transmit descriptor.

The descriptor start address must be DWORD aligned.

TPCE863 User Manual Issue 1.0.1

Page 51 of 72

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Содержание TPCE863

Страница 1: ...Channel High Speed Sync Async Serial Interface Version 1 0 User Manual Issue 1 0 1 August 2014 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 4058 0 Fax 49 0 4101 4058 19...

Страница 2: ...ment at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are sp...

Страница 3: ...Issue Description Date 1 0 0 Initial Issue September 2012 1 0 1 General Revision August 2014 TPCE863 User Manual Issue 1 0 1 Page 3 of 72...

Страница 4: ...5 IQLENR1 Interrupt Queue Length Register 1 27 5 5 6 IQSCCiRXBAR Interrupt Queue SCCi Receiver Base Address Register 28 5 5 7 IQSCCiTXBAR Interrupt Queue SCCi Transmitter Base Address Register 28 5 5...

Страница 5: ...ller 55 6 2 1 DMA Controller initiated Interrupts 56 6 2 2 Interrupt Vector Description 57 6 2 2 1 Configuration Interrupt Vector 57 6 2 2 2 DMA Controller Interrupt Vector 57 6 2 2 3 SCC Interrupt Ve...

Страница 6: ...9 MODULE MANAGEMENT 70 9 1 On Board LEDs 70 10 PIN ASSIGNMENT I O CONNECTOR 71 10 1 Front Panel I O Connector 71 TPCE863 User Manual Issue 1 0 1 Page 6 of 72...

Страница 7: ...RESS MODE 0 60 FIGURE 7 2 CLOCK SOURCES 63 FIGURE 7 3 NRZ AND NRZI DATA ENCODING 64 FIGURE 7 4 FM0 AND FM1 DATA ENCODING 65 FIGURE 7 5 MANCHESTER DATA ENCODING 65 FIGURE 8 1 TRANSMIT RECEIVE CLOCK POL...

Страница 8: ...QCFGBAR REGISTER 30 TABLE 5 14 FIFO CONTROL REGISTER 1 30 TABLE 5 15 CHICFG REGISTER 32 TABLE 5 16 CHIBRDA REGISTER 33 TABLE 5 17 CHIBTDA REGISTER 33 TABLE 5 18 CHIFRDA REGISTER 33 TABLE 5 19 CHIFTDA...

Страница 9: ...URATION INTERRUPT VECTOR 57 TABLE 6 7 DMA INTERRUPT VECTOR 57 TABLE 6 8 DMA INTERRUPT VECTOR SOURCE IDS 57 TABLE 6 9 SCC INTERRUPT VECTOR 59 TABLE 6 10 SCC INTERRUPT VECTOR SOURCE IDS 59 TABLE 7 1 PRO...

Страница 10: ...scillator provides standard asynchronous baud rates A 24 MHz and a 10 MHz oscillator are provided for other synchronous baud rates Additionally each channel provides various interrupt sources generate...

Страница 11: ...to 16 Byte SCC Receive FIFO per channel 16 Byte Data Rates Synchronous 10 Mbit s Non DPLL Modes 2 Mbit s DPLL Modes Asynchronous 2 Mbit s I O Connector Front panel HD68 SCSI 3 Type Connector AMP 78708...

Страница 12: ...ructions ESD Protection 3 1 The TPCE863 is sensitive to Electrostatic Discharge ESD Packing unpacking and all other handling of the TPCE863 has to be done in an ESD EOS protected Area TPCE863 User Man...

Страница 13: ...board PCI bus i e the FPGA PI7C9X111SL PCIe PCI Bridge 4 2 The PI7C9X111SL is a PCI Express to PCI reversible bridge On the TPCE863 the PI7C9X111SL is used in transparent forward mode only 4 2 1 PI7C...

Страница 14: ...econdary Latency Timer Subordinate Bus Number Secondary Bus Number Primary Bus Number 00 00 00 00 0x1C Secondary Status I O Limit I O Base 0200 01 01 0x20 Memory Limit Memory Base 0000 8000 0x24 Prefe...

Страница 15: ...Ac Subsystem ID Subsystem Vendor ID 0000 0000 0xB0 PCI Express Capabilities PCI Express Next Capability Pointer PCI Express Capability ID 0071 D810 0xB4 Device Capabilities 0000 0022 0xB8 PCI Express...

Страница 16: ...ications are Enable Lane Polarity Inversion disabled by default SCC FPGA 4 3 The Serial Communication Controller SCC FPGA resides on the on board 32 bit 33 MHz PCI bus and is the only other PCI device...

Страница 17: ...igh speed serial communication controller SCC FPGA 0x14 Base Address Register 1 not used 0x18 Base Address Register 2 not used 0x1C Base Address Register 3 not used 0x20 Base Address Register 4 not us...

Страница 18: ...Space PCI Space Mapping Size Byte Port Width Bit Endian Mode Description 0 0x10 MEM 2048 32 Little Register Space Table 5 1 Register Space Register Map 5 2 Offset to PCI Base Address Addresses range...

Страница 19: ...TX Base Address Register 0x0034 FIFOCR4 FIFO Control Register 4 0x0038 reserved 0x003C IQCFGBAR IQ CFG Base Address Register 0x0040 reserved 0x0044 FIFOCR1 FIFO Control Register 1 0x0048 reserved 0x00...

Страница 20: ...0DC reserved 0x00E0 CH0LTDA Channel 0 Last Tx Descr Address 0x00E4 CH1LTDA Channel 1 Last Tx Descr Address 0x00E8 CH2LTDA Channel 2 Last Tx Descr Address 0x00EC CH3LTDA Channel 3 Last Tx Descr Address...

Страница 21: ...ed registers Each SCC channel register set contains the following registers Register Offset Register Name 0x00 CMDR Command Register 0x04 STAR Status Register 0x08 CCR0 Channel Configuration Register...

Страница 22: ...igure the corresponding interrupt queue if action request bit AR is set to 1 1 Causes the DMA interrupt controller to configure re configure the corresponding interrupt queue if action request bit AR...

Страница 23: ...rupt Queue SCC2 Transmit see above R W 0 25 CFGIQSCC1TX Configure Interrupt Queue SCC1 Transmit see above R W 0 24 CFGIQSCC0TX Configure Interrupt Queue SCC0 Transmit see above R W 0 23 22 Reserved 0...

Страница 24: ...the configuration word DWORD 0 and next descriptor address DWORD 1 of the current descriptor again If the HOLD bit is detected cleared 0 the DMA controller will branch to the next descriptor When the...

Страница 25: ...ISCC3RX Interrupt Indication Queue SCC3 Receive R C 0 30 IISCC2RX Interrupt Indication Queue SCC2 Receive R C 0 29 IISCC1RX Interrupt Indication Queue SCC1 Receive R C 0 28 IISCC0RX Interrupt Indicati...

Страница 26: ...an action request 1 The last action request command was completed with an action request failed condition R C 0 0 ARACK Action Request Acknowledge Status This bit indicates that an action request comm...

Страница 27: ...gth R W 0 11 8 IQSCC1TXLEN Interrupt Queue SCC2 Transmit Length R W 0 7 4 IQSCC2TXLEN Interrupt Queue SCC1 Transmit Length R W 0 3 0 IQSCC3TXLEN Interrupt Queue SCC0 Transmit Length These bit fields d...

Страница 28: ...s of Receive Interrupt Queue R W 0 1 0 R 0 Table 5 10 IQSCCiRXBAR Register 5 5 7 IQSCCiTXBAR Interrupt Queue SCCi Transmitter Base Address Register i 0 3 0x0024 0x0028 0x002C 0x0030 Bit Symbol Descrip...

Страница 29: ...ber of valid data words belonging to a frame in the main transmit FIFO is greater than the threshold the DMAC will provide transmit data to the corresponding SCC Once having started serving data for a...

Страница 30: ...3 Main Transmit FIFO Size Depth Channel 3 R W 111 23 19 Reserved 0 for reads R 0 18 16 TFSIZE2 Main Transmit FIFO Size Depth Channel 2 R W 111 15 9 Reserved 0 for reads R 0 10 8 TFSIZE1 Main Transmit...

Страница 31: ...n is enabled for the dedicated DMA transmit channel 1 FI interrupt generation is disabled for the dedicated DMA transmit channel R W 0 25 MRERR Mask Receive ERR Interrupt Channel i This bit enables di...

Страница 32: ...cally if successful This command causes the specific DMA receive channel to fetch the base descriptor address from register CHiBRDA and to branch to the corresponding descriptor Afterwards normal DMA...

Страница 33: ...3 0x0098 0x009C 0x00A0 0x00A4 Bit Symbol Description Access Reset Value 31 2 CHiFRDA DMAC enters the PCI Base Address of the current Receive Descriptor R 0 1 0 R 0 Table 5 18 CHiFRDA Register 5 5 15...

Страница 34: ...sion Register 0x00F0 Bit Symbol Description Access Reset Value 31 16 SPC_ID Reserved 0 for reads or special customer ID register R 0 15 0 VER FPGA Logic Version R 0x0007 Table 5 22 Version Register 5...

Страница 35: ...a PCI transaction R 0x00 7 RCNTCLR Reset maximum number of retries Self clearing command bit R W 0 6 INI_HALT Initiator State Machine is stopped due to PCI transaction abort R 0 5 INI_REL Release the...

Страница 36: ...ter all changes in protocol mode configurations e g switching between the protocol engines HDLC ASYNC or sub modes of HDLC Note A transmit clock must be present R W 0 23 17 Reserved 0 for reads R 0 16...

Страница 37: ...be present Optionally this input can be programmed to generate an interrupt on signal level changes R 20 Reserved 0 for reads R 0 19 DPLA DPLL Asynchronous This bit is only valid if the receive clock...

Страница 38: ...SR read accesses 1 Masked interrupt status bits are visible in the ISR To clear these interrupt flags the host CPU must write 1 to the corresponding ISR bit Note Masked interrupts will not generate an...

Страница 39: ...unction of RTS depends on RTS and FRTS RTS FRTS 0 0 Pin RTS is controlled autonomously RTS is asserted low when data is available in the SCC transmit FIFO 0 1 Pin RTS is controlled autonomously RTS is...

Страница 40: ...h async isochr Determines the time out period If there is no receive line activity for the configured period of time a time out indication is generated if enabled via bit TOIE The period of time is pr...

Страница 41: ...condition is cleared XBRK 0 A transmit reset command bit XRES in register CMDR does NOT clear the break condition automatically R W 0 24 asyn STOP Stop Bit Number async isochr 0 1 stop bit per charact...

Страница 42: ...PCI bus bursts 1 Maximum PCI bus write burst length for receive data is set to 1 DWORD forward receive data to the PCI bus as soon as possible R W 0 17 4 Reserved 0 for reads R 0 3 ITF Interframe Time...

Страница 43: ...11 8 0 15 The alternative is to set k 1 directly as a 21 bit wide value when BRR 31 1 k BRR 20 0 1 respectively BRR 20 0 k 1 5 6 7 TCR Termination Character Register 0x0148 0x01C8 0x0248 0x02C8 Bit Sy...

Страница 44: ...iption R 1 18 ALLS R W 1 17 R 1 16 hdlc XDU R W 1 16 asyn R 1 15 R 1 14 CSC R W 1 13 10 R 1 9 asyn BRK R W 1 8 asyn BRKT R W 1 7 asyn TCD R W 1 6 asyn TIME R W 1 5 asyn PERR R W 1 4 asyn FERR R W 1 9...

Страница 45: ...reads R 0 9 asyn BRK Break Interrupt async isochr This bit is set to 1 if a break condition was detected on the receive line i e a low level for a time equal to character length parity bit stop bit s...

Страница 46: ...n has been regained again If the transmitter is supplied with a clock derived from the DPLL transmission is also interrupted R C 0 2 CDSC Carrier Detect Status Change Interrupt This bit is set to 1 if...

Страница 47: ...e to be mirrored to get the original data bytes R W 0 18 DTR3 Data Terminal Ready Channel 3 Only on channel 3 R W 0 17 CDOUT CD Output Value R W 0 16 CDDIR CD Direction 0 CD is input 1 CD is output R...

Страница 48: ...rmal function 1 TxC Output Enabled on RTS R W 0 2 0 MODE Transceiver Mode M2 M0 see following table R W 111 Table 5 33 Additional Configuration Register The input frequency range of the x4 clock multi...

Страница 49: ...and linking descriptors and buffers as required during runtime or by static predefined memory structures e g ring chained lists the last descriptor points back to the first descriptor A mix of predef...

Страница 50: ...host and read by the corresponding DMA channel using a burst transaction when requested by the host either via an AR Action Request command or a transmit poll command or after branching from previous...

Страница 51: ...s deactivated for transmit direction as long as the microprocessor does not request an activation via the CMDR register NO Byte Number NO defines the number of bytes stored in the data section to be t...

Страница 52: ...so written by the DMA channel but only for descriptors containing the first or only data section of an HDLC frame or data block It is a pointer to the last descriptor containing the frame or block end...

Страница 53: ...be valid Descriptor start address must be DWORD aligned Receive Data Pointer This 32 bit pointer contains the start address of the receive data section for a receive descriptor The start address must...

Страница 54: ...ive descriptor or by a FRDA LRDA condition Frame End Descriptor Pointer This 32 bit pointer is only valid in the descriptor which contains the data pointer to the first data section of an HDLC frame o...

Страница 55: ...DWORDs deep The interrupt controller transfers interrupt vectors to one of nine circular interrupt queues located in the shared system memory depending on the source ID of each interrupt vector In add...

Страница 56: ...nexpected descriptor configuration Receive descriptor ERR is generated if receive data cannot be transferred to the shared memory completely because the frame block does not fit into the current data...

Страница 57: ...successfully ARACK 0 No action request was performed or completed successfully ARACK 1 The last action request command was completed successfully 6 2 2 2 DMA Controller Interrupt Vector DMA controller...

Страница 58: ...mit direction Issued if the FE bit is detected in the transmit descriptor It is set when the DMAC branches to the next transmit descriptor belonging to a new frame or when HOLD bit is set in conjuncti...

Страница 59: ...13 10 9 8 7 6 5 4 3 2 1 0 0 CSC 0 BRK BRKT TCD TIME PERR FERR PLLA CDSC RFO 0 Table 6 9 SCC Interrupt Vector Source ID Description 000 Receive Channel 0 Interrupt Vector IQSCC0RX 001 Receive Channel 1...

Страница 60: ...Table 7 1 Protocol Modes Extended transparent is a fully bit transparent transmit reception mode which is treated as a sub mode of the HDLC block 7 1 1 HDLC Mode The HDLC transmitter does not generat...

Страница 61: ...ncluding start bit The synchronization lasts for one character the next incoming character causes a new synchronization As a result the demand for high clock accuracy is reduced Two communication stat...

Страница 62: ...FIFO The Break interrupt BRK is generated if enabled The break condition will be present until a 1 is received which is indicated by the Break Terminated interrupt BRKT 7 1 2 6 Flow Control Transmitte...

Страница 63: ...multiplier is provided The input frequency range of the internal x4 clock multiplier is 4 5 MHz to 28 MHz these values must never be exceeded to ensure proper function of the clock multiplier Figure 7...

Страница 64: ...o Zero Inverted NRZI FM0 known as Bi Phase Space FM1 known as Bi Phase Mark Manchester known as Bi Phase NRZ data encoding must be used for asynchronous mode 7 4 1 NRZ and NRZI Encoding NRZ The signal...

Страница 65: ...ell whereas a logical 0 has none The transmit clock precedes the receive clock by 90 Transmit Clock FM0 1 0 0 1 1 Receiver Clock FM1 Figure 7 4 FM0 and FM1 Data Encoding 7 4 3 Manchester Encoding In t...

Страница 66: ...clock from the incoming data stream and to adjust its phase to the incoming data in order to provide optimal bit sampling The DPLL reference clock is the baud rate generator output clock which must be...

Страница 67: ...configuration information used by the software drivers and must not be overwritten The other addresses 0x60 0x7F are user programmable The configuration EEPROM contains the following data Vendor ID V...

Страница 68: ...6 0x1E Reserved 0x1F Programmable Interfaces 0x000F 0x20 Max Data Rate RS232 high 0x0001 0x21 Max Data Rate RS232 low 0xF400 0x22 Max Data Rate RS422 high 0x0098 0x23 Max Data Rate RS422 low 0x9680 0x...

Страница 69: ...INV 1 RS232TypeCableInterface RS232TypeCableInterface TXC TXD RXC RXD TXCINV 0 RXCINV 0 RS422TypeCableInterface TXC TXD RXC RXD TXCINV 1 RXCINV 1 RS422TypeCableInterface RXCINV 1 BoardLevel BoardLevel...

Страница 70: ...iguration state LED Color Description DONE Green Shows whether the FPGA has configured or not 3 3 Green PCIe Connector provided 3 3V voltage is valid 2 5 Green On board 2 5V voltage is in desired rang...

Страница 71: ...10 Pin Assignment I O Connector Front Panel I O Connector 10 1 AMP 787082 7 or compatible Figure 10 1 Front Panel I O Connector Numbering TPCE863 User Manual Issue 1 0 1 Page 71 of 72...

Страница 72: ...RXCA 16 RXCB 50 RXCB 17 CDA 2 51 CDA 3 18 CDB 52 CDB 19 RXDA 53 RXDA 20 RTSA 54 RTSA 21 TXDA 55 TXDA 22 CTSA 56 CTSA 23 RTSB 57 RTSB 24 CTSB 58 CTSB 25 GND 59 GND 26 TXDB 60 TXDB 27 RXDB 61 RXDB 28 TX...

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