5.6.3 CCR0 – Channel Configuration Register 0
(0x0108, 0x0188, 0x0208, 0x0288)
Bit
Symbol Description
Access
Reset
Value
31:23
-
Reserved (0 for reads)
R
0
22:20
SC
Serial Port Configuration
‘000’: NRZ data encoding
‘010’: NRZI data encoding
‘100’: FM0 data encoding
‘101’: FM1 data encoding
‘110’: Manchester data encoding
others: reserved
R/W
000
19:18
-
Reserved (0 for reads)
R
0
17:16
SM
Serial Port Mode
Selects the protocol engine:
‘00’: HDLC synchronous
‘01’: reserved
‘10’: reserved
‘11’: Asynchronous
R/W
00
15:13
-
Reserved (0 for reads)
R
0
12
VIS
Masked Interrupts Visible
’0’: Masked interrupt status bits are not visible on interrupt
status register (ISR) read accesses.
’1’: Masked interrupt status bits are visible in the ISR. To
clear these interrupt flags, the host CPU must write ‘1’
to the corresponding ISR bit.
Note: Masked interrupts will not generate an interrupt vector to the
interrupt controller.
R/W
0
11:8
-
Reserved (0 for reads)
R
0
7
BCR
Bit Clock Rate (async/isochr)
‘0’: Isochronous (Bit Clock Rate x1).
I.e. Asynchronous without oversampling.
Transmitter/Receiver Clock Rate is Data Bit Rate x1. Bits
are sampled once.
‘1’: Standard asynchronous (Bit Clock Rate x16).
I.e. Asynchronous with 16x oversampling.
Transmitter/Receiver Clock Rate is Data Bit Rate x16. Bits
are sampled 16 times. The result is determined by a
majority decision of 3 samples around the bit center. NRZ
encoding has to be selected.
R/W
0
6
-
Reserved (0 for reads)
R
0
TPCE863 User Manual Issue 1.0.1
Page 38 of 72
