TIP810 Version 3.0 User Manual Issue 3.0.4
Page 14 of 19
Register (function in Operating/Reset Mode)
Address
Access
. .
.
. .
.
. .
.
Internal RAM address 63 (FIFO)
0xBF
R/W
Internal RAM address 64 (TX buffer)
0xC1
R/W
. .
.
. .
.
. .
.
Internal RAM address 76 (TX buffer)
0xD9
R/W
Internal RAM address 77 (free)
0xDA
R/W
Internal RAM address 78 (free)
0xDB
R/W
Internal RAM address 79 (free)
0xDC
R/W
0x00 0xDD
R
0x00 0xDE
R
. .
.
. .
.
. .
.
0x00 0xFF
R
Table 5-2 : "PeliCAN"-Mode Register Set
R/(W) : These Registers can only be written in Reset Mode!
R/[W] : These Register can only be written in Operating Mode!
R : Read only
W : Write only
When operating in "PeliCAN"-Mode the Interrupt Vector Register is still mapped to address
offset 0x41 in the IP I/O Space.
