TIP810 Version 3.0 User Manual Issue 3.0.4
Page 12 of 19
5.1 "BasiCAN" Mode Register Set
The lower 32bytes of the SJA1000 register space (address offset 0x01 – 0x3F) are accessible in the
IP I/O Space
. This covers the complete "BasiCAN" mode register set.
All registers are byte sized. Read accesses to write-only registers will result in a value of 0xFF on the
data bus.
Register (function in Operating/Reset Mode)
Address
Access
Control Register (control/control) 0x01
R/W
Command Register
0x03
W
Status Register (status/status)
0x05
R
Interrupt Register (interrupt/interrupt)
0x07
R
Acceptance Code Register (0xFF/acceptance code)
0x09
R/(W)
Acceptance Mask Register (0xFF/acceptance mask)
0x0B
R/(W)
Bus Timing Register 0 (0xFF/Bus Timing 0)
0x0D
R/(W)
Bus Timing Register 1(0xFF/Bus Timing 1)
0x0F
R/(W)
Output Control Register (0xFF/Output Control)
0x11
R/(W)
Test Register
0x13
R
Transmit Buffer Identifier (identifier 10 to 3/0xFF
0x15
R/W
Transmit Buffer RTR, Data length (identifier 2 to 0/0xFF)
0x17
R/W
Transmit Buffer Byte 1 (data byte 1/0xFF)
0x19
R/[W]
Transmit Buffer Byte 2 (data byte 2/0xFF)
0x1B
R/[W]
Transmit Buffer Byte 3 (data byte 3/0xFF)
0x1D
R/[W]
Transmit Buffer Byte 4 (data byte 4/0xFF)
0x1F
R/[W]
Transmit Buffer Byte 5 (data byte 5/0xFF)
0x21
R/[W]
Transmit Buffer Byte 6 (data byte 6/0xFF)
0x23
R/[W]
Transmit Buffer Byte 7 (data byte 7/0xFF)
0x25
R/[W]
Transmit Buffer Byte 8 (data byte 8/0xFF)
0x27
R/[W]
Receive Buffer Identifier (identifier 10 to 3/identifier 10 to 3)
0x29
R/W
Receive Buffer RTR, Data length (identifier 2 to 0/identifier 2 to 0)
0x2B
R/W
Receive Buffer Byte 1 (data byte 1/data byte 1)
0x2D
R/W
Receive Buffer Byte 2 (data byte 2/data byte 2)
0x2F
R/W
Receive Buffer Byte 3 (data byte 3/data byte 3)
0x31
R/W
Receive Buffer Byte 4 (data byte 4/data byte 4)
0x33
R/W
Receive Buffer Byte 5 (data byte 5/data byte 5)
0x35
R/W
Receive Buffer Byte 6 (data byte 6/data byte 6)
0x37
R/W
Receive Buffer Byte 7 (data byte 7/data byte 7)
0x39
R/W
Receive Buffer Byte 8 (data byte 8/data byte 8)
0x3B
R/W
Reserved (0xFF/0xFF)
0x3D
R
Clock Divider Register
0x3F
R/W
Table 5-1 : "BasiCAN" Mode Register Set
